Patents by Inventor Raymundo M. Camenforte
Raymundo M. Camenforte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20230402373Abstract: Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.Type: ApplicationFiled: June 21, 2023Publication date: December 14, 2023Inventors: Sanjay Dabral, Jun Zhai, Kunzhong Hu, Raymundo M. Camenforte
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Patent number: 11728266Abstract: Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.Type: GrantFiled: December 23, 2020Date of Patent: August 15, 2023Assignee: Apple Inc.Inventors: Sanjay Dabral, Jun Zhai, Kunzhong Hu, Raymundo M. Camenforte
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Publication number: 20230178458Abstract: Package structures, modules containing such packages and methods of manufacture. are described. In an embodiment, a package includes a plurality of terminal pads, a plurality of passive components bonded to top sides of the plurality of terminal pads, a die bonded to top sides of the plurality of passive components and a molding compound encapsulating at least the plurality of passive components and the die.Type: ApplicationFiled: December 8, 2021Publication date: June 8, 2023Inventors: Kumar Nagarajan, Flynn P. Carson, Karthik Shanmugam, Menglu Li, Raymundo M. Camenforte, Scott D. Morrison
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Patent number: 11395408Abstract: Wafer level passive array packages and modules are described. In an embodiment, a module includes a circuit board, and a package mounted on the circuit board in which the package includes a plurality of passive components bonded to a bottom side of the die and a plurality of landing pads of the circuit board.Type: GrantFiled: August 28, 2020Date of Patent: July 19, 2022Assignee: Apple Inc.Inventors: Scott D. Morrison, Karthik Shanmugam, Raymundo M. Camenforte, Rakshit Agrawal, Flynn P. Carson, Kiranjit Dhaliwal
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Publication number: 20220199517Abstract: Multi-die structures with die-to-die routing are described. In an embodiment, each die is patterned into the same semiconductor substrate, and the dies may be interconnected with die-to-die routing during back-end wafer processing. Partial metallic seals may be formed to accommodate the die-to-die routing, programmable dicing, and various combinations of full metallic seals and partial metallic seals can be formed. This may also be extended to three dimensional structures formed using wafer-on-wafer or chip-on-wafer techniques.Type: ApplicationFiled: December 23, 2020Publication date: June 23, 2022Inventors: Sanjay Dabral, Jun Zhai, Kunzhong Hu, Raymundo M. Camenforte
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Publication number: 20220157680Abstract: Flexible packages and electronic devices with integrated flexible packages are described. In an embodiment, a flexibly package includes a first die and a second die encapsulated in a molding compound layer. A compliant redistribution layer (RDL) spans the molding compound layer and both dies, and includes electrical routing formed directly on landing pads of the dies. A notch is formed in the molding compound layer between the dies to facilitate flexure of the compliant RDL.Type: ApplicationFiled: November 19, 2020Publication date: May 19, 2022Inventors: Karthik Shanmugam, Flynn P. Carson, Jun Zhai, Raymundo M. Camenforte, Menglu Li
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Publication number: 20220071013Abstract: Wafer level passive array packages, modules, and methods of fabrication are described. In an embodiment, a module includes a circuit board, and a package mounted on the circuit board in which the package includes a plurality of passive components bonded to a bottom side of the die and a plurality of landing pads of the circuit board.Type: ApplicationFiled: August 28, 2020Publication date: March 3, 2022Inventors: Scott D. Morrison, Karthik Shanmugam, Raymundo M. Camenforte, Rakshit Agrawal, Flynn P. Carson, Kiranjit Dhaliwal
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Patent number: 8815642Abstract: A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving.Type: GrantFiled: October 4, 2013Date of Patent: August 26, 2014Assignee: Texas Instruments IncorporatedInventors: Jeffrey Alan West, Margaret Simmons-Matthews, Raymundo M. Camenforte
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Publication number: 20140038359Abstract: A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving.Type: ApplicationFiled: October 4, 2013Publication date: February 6, 2014Applicant: Texas Instruments IncorporatedInventors: Jeffrey Alan West, Margaret Simmons-Matthews, Raymundo M. Camenforte
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Patent number: 8575758Abstract: A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving.Type: GrantFiled: August 4, 2011Date of Patent: November 5, 2013Assignee: Texas Instruments IncorporatedInventors: Jeffrey Alan West, Margaret Simmons-Matthews, Raymundo M. Camenforte
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Publication number: 20130032946Abstract: A method of forming stacked die devices includes attaching first semiconductor die onto a wafer to form a reconstituted wafer, and then bonding second semiconductor die onto the first semiconductor die to form a plurality of singulated stacked die devices on the wafer. A support tape is attached to a bottomside of the second semiconductor die. A dicing tape is attached to the wafer. The wafer is laser irradiated before or after attachment of the dicing tape at intended dicing lanes that align with gaps between the first semiconductor die to mechanically weaken the wafer at the intended dicing lanes, but not cut through the wafer. The dicing tape is pulled to cleave the wafer into a plurality of singulated portions to form a plurality of singulated stacked die devices attached to the singulated wafer portions by the dicing tape. The support tape is removed prior to cleaving.Type: ApplicationFiled: August 4, 2011Publication date: February 7, 2013Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: JEFFREY ALAN WEST, MARGARET SIMMONS-MATTHEWS, RAYMUNDO M. CAMENFORTE
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Patent number: 6791346Abstract: A method and apparatus for handling small semiconductor devices in the testing of these devices. Multiple devices are mounted within a device strip carrier and are positioned in the testing position. This positioning of the device strip carriers is performed using device strip carrier alignment tools; the device strip carrier can readily be repositioned with respect to the test head/probe card for testing of multiple devices contained within the device strip carrier.Type: GrantFiled: May 8, 2002Date of Patent: September 14, 2004Assignee: St. Assembly Test Services Pte LtdInventors: Rajiv Mehta, Liop-Jin Yap, Raymundo M. Camenforte, Chee-Keong Tan
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Patent number: 6759752Abstract: A package is provided for the mounting of IC devices. The IC die is bonded to metal traces contained in a flexible tape, the IC die with the flexible tape is attached to a stiffener (heat spreader), the various heat conducting interfaces are cured and solder balls are attached to another surface of the flexible tape.Type: GrantFiled: February 20, 2003Date of Patent: July 6, 2004Assignee: St Assembly Test Services Ltd.Inventors: Raymundo M. Camenforte, John Briar
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Patent number: 6744125Abstract: A new method and package is provided for the packaging of semiconductor devices. The method and package starts with a semiconductor substrate, the substrate is pre-baked. In the first embodiment of the invention, a copper foil is attached to the substrate, in the second embodiment of the invention a adhesive film is attached to the substrate. Processing then continues by attaching the die to the copper foil under the first embodiment of the invention and to the film under the second embodiment of the invention. After this the processing continues identically for the two embodiments of the invention with steps of curing, plasma cleaning, wire bonding, optical inspection, plasma cleaning and providing a molding around the die and the wires connected to the die. For the second embodiment of the invention, the film is now detached and replaced with a copper foil.Type: GrantFiled: January 9, 2003Date of Patent: June 1, 2004Assignee: St. Assembly Test Services Ltd.Inventors: Raymundo M. Camenforte, Dioscoro A. Merilo, Seng Guan Chow
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Patent number: 6617525Abstract: A molded flexible circuit assembly and method of forming a molded flexible circuit assembly which use a molded stiffener, and do not require any additional type of stiffener, are described. A molded stiffener is formed on a flexible tape at the same time molded encapsulation units are formed to encapsulate circuit die which are attached to the flexible tape. The molded stiffeners provide adequate rigidity for processing of the molded flexible circuit assembly. When the stiffeners are no longer needed they are removed at the same time the mold runners are removed. No additional processing steps are required for either the formation or removal of the molded stiffeners.Type: GrantFiled: January 14, 2002Date of Patent: September 9, 2003Assignee: St. Assembly Test Services Ltd.Inventors: John Briar, Raymundo M. Camenforte
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Publication number: 20030151148Abstract: A new package is provided for the mounting of IC devices. The IC die is bonded to metal traces contained in a flexible tape, the IC die with the flexible tape is attached to a stiffener (heat spreader), the various heat conducting interfaces are cured and solder balls are attached to another surface of the flexible tape.Type: ApplicationFiled: February 20, 2003Publication date: August 14, 2003Applicant: ST ASSEMBLY TEST SERVICES PTE LTDInventors: Raymundo M. Camenforte, John Briar
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Publication number: 20030143777Abstract: A new method and package is provided for the packaging of semiconductor devices. The method and package starts with a semiconductor substrate, the substrate is pre-baked. In the first embodiment of the invention, a copper foil is attached to the substrate, in the second embodiment of the invention a adhesive film is attached to the substrate. Processing then continues by attaching the die to the copper foil under the first embodiment of the invention and to the film under the second embodiment of the invention. After this the processing continues identically for the two embodiments of the invention with steps of curing, plasma cleaning, wire bonding, optical inspection, plasma cleaning and providing a molding around the die and the wires connected to the die. For the second embodiment of the invention, the film is now detached and replaced with a copper foil.Type: ApplicationFiled: January 9, 2003Publication date: July 31, 2003Applicant: ST Assembly Test Services Ltd.Inventors: Raymundo M. Camenforte, Dioscoro A. Merilo, Seng Guan Chow
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Patent number: 6544812Abstract: A package is provided for the mounting of IC devices. The IC die is bonded to metal traces contained in a flexible tape, the IC die with the flexible tape is attached to a stiffener (heat spreader), the various heat conducting interfaces are cured and solder balls are attached to another surface of the flexible tape.Type: GrantFiled: November 6, 2000Date of Patent: April 8, 2003Assignee: St Assembly Test Service Ltd.Inventors: Raymundo M. Camenforte, John Briar
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Patent number: 6537848Abstract: In a first embodiment of the invention, a copper foil is attached to a substrate, in the second embodiment of the invention a adhesive film is attached to a substrate. Processing then continues by attaching the die to the copper foil/adhesive film. After this the processing continues identically for the two embodiments of the invention, interrupted by, for the second embodiment of the invention, detaching the film and replacing the film with a copper foil.Type: GrantFiled: May 30, 2001Date of Patent: March 25, 2003Assignee: St. Assembly Test Services Ltd.Inventors: Raymundo M. Camenforte, Dioscoro A. Merilo, Seng Guan Chow
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Patent number: 6535004Abstract: A method and apparatus for handling small semiconductor devices in the testing of these devices. Multiple devices are mounted within a device strip carrier and are positioned in the testing position. This positioning of the device strip carriers is performed using device strip carrier alignment tools; the device strip carrier can readily be repositioned with respect to the test head/probe card for testing of multiple devices contained within the device strip carrier.Type: GrantFiled: May 8, 2002Date of Patent: March 18, 2003Assignee: ST Assembly Test Service Ltd.Inventors: Rajiv Mehta, Liop-Jin Yap, Raymundo M. Camenforte, Chee-Keong Tan