Patents by Inventor Raz Reshef
Raz Reshef has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11979676Abstract: A robust analog counter that may include an output capacitor having a first capacitance, and a charging unit (CU) that is configured to determine that an event to be counted occurred, and charge the output capacitor at a first current and during a output capacitor charging period, wherein a duration of the output capacitor charging period is proportional to the first capacitance, thereby increasing an output voltage of the output capacitor by a voltage quote that is indifferent to at least one out of process variation, temperature or power supply voltage value.Type: GrantFiled: April 26, 2022Date of Patent: May 7, 2024Assignee: TOWER SEMICONDUCTOR LTD.Inventors: Raz Reshef, Dmitry Dain
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Patent number: 11962919Abstract: For example, analog pixel circuitry may include a first input to input an analog pixel signal of the pixel; Sample and Hold (SH) circuitry to provide an analog sample of the pixel based on the analog pixel signal; one or more second inputs to input analog samples of one or more binning pixels, respectively; a plurality of capacitors having capacitor outputs connected to a common output terminal, wherein a capacitor input of a first capacitor is connected to an input terminal to input the analog sample of the pixel from the SH circuitry, wherein capacitor inputs of one or more second capacitors are connected to the one or more second inputs, respectively; and an amplifier configured to provide an amplified analog signal by amplifying an analog signal from the common output terminal.Type: GrantFiled: July 24, 2022Date of Patent: April 16, 2024Assignee: TOWER SEMICONDUCTOR LTD.Inventors: Alexander Faingersh, Vered Antebi, Raz Reshef
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Publication number: 20240031693Abstract: For example, analog pixel circuitry may include a first input to input an analog pixel signal of the pixel; Sample and Hold (SH) circuitry to provide an analog sample of the pixel based on the analog pixel signal; one or more second inputs to input analog samples of one or more binning pixels, respectively; a plurality of capacitors having capacitor outputs connected to a common output terminal, wherein a capacitor input of a first capacitor is connected to an input terminal to input the analog sample of the pixel from the SH circuitry, wherein capacitor inputs of one or more second capacitors are connected to the one or more second inputs, respectively; and an amplifier configured to provide an amplified analog signal by amplifying an analog signal from the common output terminal.Type: ApplicationFiled: July 24, 2022Publication date: January 25, 2024Applicant: TOWER SEMICONDUCTOR LTD.Inventors: Alexander Faingersh, Vered Antebi, Raz Reshef
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Publication number: 20230345149Abstract: A robust analog counter that may include an output capacitor having a first capacitance, and a charging unit (CU) that is configured to determine that an event to be counted occurred, and charge the output capacitor at a first current and during a output capacitor charging period, wherein a duration of the output capacitor charging period is proportional to the first capacitance, thereby increasing an output voltage of the output capacitor by a voltage quote that is indifferent to at least one out of process variation, temperature or power supply voltage value.Type: ApplicationFiled: April 26, 2022Publication date: October 26, 2023Applicant: Tower Semiconductor Ltd.Inventors: Raz Reshef, Dmitry Dain
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Patent number: 10630070Abstract: A device for overcurrent protection, the device may include a main transistor that is configured to supply, via an output node, a load current to a load; a current limiting resistor; a replica transistor that is configured to provide a replica current to the current limiting resistor; wherein the replica current is smaller than the load current, wherein a value of the replica current is responsive to a value of the load current; an amplifier; a current limiting transistor; a variable signal source that is configured to output a reference signal; wherein a value of the reference signal is based on a main transistor voltage; wherein the amplifier is configured to prevent the load current from exceeding a first load current threshold by biasing the main transistor and the replica transistor with a bias signal; wherein a value of the bias signal is responsive to the reference signal and to the replica current.Type: GrantFiled: April 18, 2017Date of Patent: April 21, 2020Inventors: Alexander Faingersh, Valentin Lerner, Erez Sarig, Raz Reshef
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Publication number: 20180301896Abstract: A device for overcurrent protection, the device may include a main transistor that is configured to supply, via an output node, a load current to a load; a current limiting resistor; a replica transistor that is configured to provide a replica current to the current limiting resistor; wherein the replica current is smaller than the load current, wherein a value of the replica current is responsive to a value of the load current; an amplifier; a current limiting transistor; a variable signal source that is configured to output a reference signal; wherein a value of the reference signal is based on a main transistor voltage; wherein the amplifier is configured to prevent the load current from exceeding a first load current threshold by biasing the main transistor and the replica transistor with a bias signal; wherein a value of the bias signal is responsive to the reference signal and to the replica current.Type: ApplicationFiled: April 18, 2017Publication date: October 18, 2018Applicant: Tower Semiconductor LTD.Inventors: Alexander Faingersh, Valentin Lerner, Erez Sarig, Raz Reshef
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Patent number: 9729808Abstract: A single-exposure high dynamic range (HDR) image sensor utilizes a charge amplifier having a selectively coupled conversion capacitor to read a single photodiode charge during a multi-phase readout operation. An overflow readout is performed during the photodiode charge integration phase, and utilizes the conversion capacitor to read overflow signals indicating rapidly rising photodiode charges caused by extreme exposure conditions, which also prevents saturation of the photodiode. At the end of the integration phase, the remaining photodiode charge is then measured using two readouts: a high sensitivity readout during which the storage capacitor de-coupled to accurately measure low-light conditions, and a low sensitivity readout during which the remaining photodiode charge is stored on the storage capacitor to provide normal light image data. Final single exposure HDR image data is then calculated by summing the overflow image data with the high-sensitivity and/or the low-sensitivity image data.Type: GrantFiled: August 10, 2015Date of Patent: August 8, 2017Assignee: Tower Semiconductor Ltd.Inventors: Amos Fenigstein, Raz Reshef, Shay Alfassi, Guy Yehudian
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Patent number: 9258501Abstract: An endoscope system includes a host device and an endoscope including a very small area CMOS image sensor having only four pads (power, ground, digital in, analog out), and including an array of 4T pixels and associated control circuitry for performing correlated double sampling (CDS) to generate analog reset level and analog signal level values associated with light detected by photodiodes in each pixel. Instead of processing the analog values on-chip, the analog reset values and analog signal values are transmitted in separate sets one row at a time along with interleaved synchronization signals by way of a single analog contact pad to the host device of the endoscopic system, which uses the synchronization signals to reconstruct the sensor's internal clock in order to process the analog values. The endoscope housing thus requires only four wires and is made very small.Type: GrantFiled: March 15, 2013Date of Patent: February 9, 2016Assignee: Tower Semiconductor Ltd.Inventors: Raz Reshef, Erez Sarig, Aviad Haber, Shay Alfassi, Guy Yehudian
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Publication number: 20150350584Abstract: A single-exposure high dynamic range (HDR) image sensor utilizes a charge amplifier having a selectively coupled conversion capacitor to read a single photodiode charge during a multi-phase readout operation. An overflow readout is performed during the photodiode charge integration phase, and utilizes the conversion capacitor to read overflow signals indicating rapidly rising photodiode charges caused by extreme exposure conditions, which also prevents saturation of the photodiode. At the end of the integration phase, the remaining photodiode charge is then measured using two readouts: a high sensitivity readout during which the storage capacitor de-coupled to accurately measure low-light conditions, and a low sensitivity readout during which the remaining photodiode charge is stored on the storage capacitor to provide normal light image data. Final single exposure HDR image data is then calculated by summing the overflow image data with the high-sensitivity and/or the low-sensitivity image data.Type: ApplicationFiled: August 10, 2015Publication date: December 3, 2015Inventors: Amos Fenigstein, Raz Reshef, Shay Alfassi, Guy Yehudian
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Patent number: 9106851Abstract: A single-exposure high dynamic range (HDR) image sensor utilizes a charge amplifier having two different charge-to-voltage conversion capacitors that read a single photodiode charge during a two-phase readout operation. The first capacitor has a lower capacitance and therefore higher conversion gain (sensitivity), and the second capacitor has a higher capacitance and therefore lower conversion gain (sensitivity). The two-phase readout operation samples the photodiode charge twice, once using the high sensitivity capacitor and once using the low sensitivity capacitor. The high sensitivity readout phase provides detailed low light condition data but is saturated under brighter light conditions, and the low sensitivity readout phase provides weak data under low light conditions but provides high quality image data under brighter light conditions. The final HDR image is created by combining both high and low sensitivity images into a single image while giving each of them the correct weighted value.Type: GrantFiled: March 12, 2013Date of Patent: August 11, 2015Assignee: Tower Semiconductor Ltd.Inventors: Amos Fenigstein, Raz Reshef, Shay Alfassi, Guy Yehudian
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Publication number: 20140263950Abstract: A single-exposure high dynamic range (HDR) image sensor utilizes a charge amplifier having two different charge-to-voltage conversion capacitors that read a single photodiode charge during a two-phase readout operation. The first capacitor has a lower capacitance and therefore higher conversion gain (sensitivity), and the second capacitor has a higher capacitance and therefore lower conversion gain (sensitivity). The two-phase readout operation samples the photodiode charge twice, once using the high sensitivity capacitor and once using the low sensitivity capacitor. The high sensitivity readout phase provides detailed low light condition data but is saturated under brighter light conditions, and the low sensitivity readout phase provides weak data under low light conditions but provides high quality image data under brighter light conditions. The final HDR image is created by combining both high and low sensitivity images into a single image while giving each of them the correct weighted value.Type: ApplicationFiled: March 12, 2013Publication date: September 18, 2014Applicant: Tower Semiconductor Ltd.Inventors: Amos Fenigstein, Raz Reshef, Shay Alfassi, Guy Yehudian
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Patent number: 8536808Abstract: A modified bootstrap circuit utilized, for example, in a high voltage DC/DC CMOS buck converter to convert a high input voltage (e.g., 24V) to a regulated voltage (e.g., 4V) for use, for example, by an LED driver circuit. The bootstrap circuit utilizes a feedback diode and a PMOS switch to avoid high reverse diode voltages across a low voltage bootstrap diode. A bootstrapped buck converter implements the bootstrap circuit to generate a high gate voltage on a high-side NMOS switch during all operating phases. The PMOS switch is controlled by the NMOS switch's output voltage to pass a system voltage (e.g., 5V) through the bootstrap diode whenever the output voltage drops low (e.g., 0V), and to shut off when the output voltage subsequently rises such that the feedback diode forward biases to pass the output voltage to the anode of the bootstrap diode.Type: GrantFiled: November 23, 2011Date of Patent: September 17, 2013Assignee: Tower Semiconductor Ltd.Inventors: Erez Sarig, Raz Reshef
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Patent number: 8520100Abstract: A very small area CMOS image sensor, e.g., for an endoscopic system, includes only four pads (power, ground, digital in, analog out), and includes an array of 4T pixels and associated control circuitry for performing correlated double sampling (CDS) to generate analog reset level and analog signal level values associated with light detected by photodiodes in each pixel. Instead of processing the analog values on-chip, the analog reset values and analog signal values are transmitted in separate sets one row at a time along with interleaved synchronization signals by way of a single analog contact pad, e.g., to a host device of an endoscopic system, which uses the synchronization signals to reconstruct the sensor's internal clock in order to process the analog values. An endoscope housing incorporating the CMOS image sensor thus requires only four wires.Type: GrantFiled: September 3, 2009Date of Patent: August 27, 2013Assignee: Tower Semiconductor Ltd.Inventors: Raz Reshef, Erez Sarig, Aviad Haber, Shay Alfassi, Guy Yehudian
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Publication number: 20130127371Abstract: A modified bootstrap circuit utilized, for example, in a high voltage DC/DC CMOS buck converter to convert a high input voltage (e.g., 24V) to a regulated voltage (e.g., 4V) for use, for example, by an LED driver circuit. The bootstrap circuit utilizes a feedback diode and a PMOS switch to avoid high reverse diode voltages across a low voltage bootstrap diode. A bootstrapped buck converter implements the bootstrap circuit to generate a high gate voltage on a high-side NMOS switch during all operating phases. The PMOS switch is controlled by the NMOS switch's output voltage to pass a system voltage (e.g., 5V) through the bootstrap diode whenever the output voltage drops low (e.g., 0V), and to shut off when the output voltage subsequently rises such that the feedback diode forward biases to pass the output voltage to the anode of the bootstrap diode.Type: ApplicationFiled: November 23, 2011Publication date: May 23, 2013Applicant: Tower Semiconductor Ltd.Inventors: Erez Sarig, Raz Reshef
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Patent number: 8203111Abstract: A CMOS image sensor in which each column of pixels is connected to a signal line that is coupled to a current source, and each pixel includes a charge amplifier having a common source configuration arranged such that a charge generated by its photodiode is amplified by the charge amplifier and transmitted to readout circuitry by way of the signal line. In one embodiment the charge amplifier utilizes an NMOS transistor to couple the photodiode charge in an inverted manner to the signal line while converting the charge to a voltage through a capacitor coupled between the signal line and photodiode (i.e., forming a feedback of the NMOS amplifier transistor).Type: GrantFiled: March 23, 2009Date of Patent: June 19, 2012Assignee: Tower Semiconductor Ltd.Inventors: Raz Reshef, Amos Fenigstein, Tomer Leitner
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Publication number: 20110050874Abstract: A very small area CMOS image sensor, e.g., for an endoscopic system, includes only four pads (power, ground, digital in, analog out), and includes an array of 4T pixels and associated control circuitry for performing correlated double sampling (CDS) to generate analog reset level and analog signal level values associated with light detected by photodiodes in each pixel. Instead of processing the analog values on-chip, the analog reset values and analog signal values are transmitted in separate sets one row at a time along with interleaved synchronization signals by way of a single analog contact pad, e.g., to a host device of an endoscopic system, which uses the synchronization signals to reconstruct the sensor's internal clock in order to process the analog values. An endoscope housing incorporating the CMOS image sensor thus requires only four wires.Type: ApplicationFiled: September 3, 2009Publication date: March 3, 2011Applicant: Tower Semiconductor Ltd.Inventors: Raz Reshef, Erez Sarig, Aviad Haber, Shay Alfassi, Guy Yehudian
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Publication number: 20100237228Abstract: A CMOS image sensor in which each column of pixels is connected to a signal line that is coupled to a current source, and each pixel includes a charge amplifier having a common source configuration arranged such that a charge generated by its photodiode is amplified by the charge amplifier and transmitted to readout circuitry by way of the signal line. In one embodiment the charge amplifier utilizes an NMOS transistor to couple the photodiode charge in an inverted manner to the signal line while converting the charge to a voltage through a capacitor coupled between the signal line and photodiode (i.e., forming a feedback of the NMOS amplifier transistor).Type: ApplicationFiled: March 23, 2009Publication date: September 23, 2010Applicant: Tower Semiconductor Ltd.Inventors: Raz Reshef, Amos Fenigstein, Tomer Leitner
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Patent number: 7737390Abstract: A large image sensor structure is created by tiling a plurality of image sensor dies, wherein each of the image sensor dies includes a pixel array that extends to three edges of the die, and control circuitry located along a fourth edge of the die. None of the control circuitry required to access the pixel array (e.g., none of the row driver circuitry) is located in the pixel array, thereby enabling consistent spacing of pixels across the pixel array. Because the pixel array of each image sensor die extends to three edges of the die, the pixel array of each image sensor die can abut up to three pixel arrays in other image sensor dies to form a large image sensor structure having 2×N tiled image sensor dies.Type: GrantFiled: January 14, 2008Date of Patent: June 15, 2010Assignee: Tower Semiconductor, Ltd.Inventors: Erez Sarig, Raz Reshef, Shay Alfassi, David Cohen
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Patent number: 7609093Abstract: A current control circuit is coupled in parallel with the current paths of a differential comparator circuit to ensure that a substantially constant current is drawn from a current source during all operating phases of a comparator. The current control circuit is biased by a reference voltage, which is also used to bias a V? input terminal of the differential comparator circuit. The reference voltage is stored by a sample capacitor, which is charged by applying the reference voltage to a V+ input terminal of the differential comparator circuit while coupling an output terminal of the differential comparator circuit to the sample capacitor in a unity feedback configuration.Type: GrantFiled: August 3, 2007Date of Patent: October 27, 2009Assignee: Tower Semiconductor Ltd.Inventors: Erez Sarig, Raz Reshef
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Publication number: 20090179141Abstract: A large image sensor structure is created by tiling a plurality of image sensor dies, wherein each of the image sensor dies includes a pixel array that extends to three edges of the die, and control circuitry located along a fourth edge of the die. None of the control circuitry required to access the pixel array (e.g., none of the row driver circuitry) is located in the pixel array, thereby enabling consistent spacing of pixels across the pixel array. Because the pixel array of each image sensor die extends to three edges of the die, the pixel array of each image sensor die can abut up to three pixel arrays in other image sensor dies to form a large image sensor structure having 2×N tiled image sensor dies.Type: ApplicationFiled: January 14, 2008Publication date: July 16, 2009Applicant: Tower Semiconductor Ltd.Inventors: Erez Sarig, Raz Reshef, Shay Alfassi, David Cohen