Patents by Inventor Razak Hossain
Razak Hossain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240106623Abstract: Aspects described herein include devices and methods for phase tracking and correction using sampling. One aspect includes a wireless communication apparatus having an analog 1-bit sampler configured to sample a phase locked loop (PLL) output signal using a PLL reference clock to generate 1-bit samples and a digital phase computation and control circuit configured to receive the 1-bit samples from the analog 1-bit sampler and apply phase corrections to the PLL based on a phase error derived from the 1-bit samples.Type: ApplicationFiled: September 23, 2022Publication date: March 28, 2024Inventors: Gang LIU, Xiaotie WU, Razak HOSSAIN, Marco ZANUSO, Yiwu TANG
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Publication number: 20240097689Abstract: Aspects of the present disclosure provide techniques and apparatus for synchronizing phase-locked loop (PLL) circuits. An example method of operating PLL circuits includes obtaining an indication to perform a synchronizing action at a first PLL circuit and a second PLL circuit; and performing the synchronizing action at the first PLL circuit and the second PLL circuit in response to obtaining the indication.Type: ApplicationFiled: September 19, 2022Publication date: March 21, 2024Inventors: Jianjun YU, Tomas O'SULLIVAN, Razak HOSSAIN, Lai Kan LEUNG
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Patent number: 11595028Abstract: An apparatus can implement a frequency doubler with duty cycle correction in conjunction with, for instance, a phase-locked loop (PLL) to decrease phase noise. In an example aspect, an apparatus has a frequency doubler including a signal combiner, a first signal pathway, and a second signal pathway. The frequency doubler also includes a doubler input node and a doubler output node. The signal combiner is coupled to the doubler output node. The first signal pathway is coupled between the doubler input node and the signal combiner and includes a first adjustable delay cell. The second signal pathway is also coupled between the doubler input node and the signal combiner and includes a second adjustable delay cell.Type: GrantFiled: June 29, 2021Date of Patent: February 28, 2023Assignee: QUALCOMM IncorporatedInventors: Masoud Moslehi Bajestan, Marco Zanuso, Razak Hossain, Hasnain Lakdawala
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Patent number: 11411569Abstract: An apparatus implements a multiplying delay-locked loop (MDLL) including a sampler to be calibrated. In an example aspect, an apparatus includes an MDLL and a sampler calibrator. The MDLL includes a locked-loop feedforward path with a sampler, a control output, a feedback input, and a reference input coupled to a reference signal source. The MDLL also includes a VCO, a multiplexer, and a divider. The VCO includes a VCO input, a VCO output, and a control input coupled to the control output. The multiplexer includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the VCO input. The divider is coupled between the VCO output and the feedback input. The sampler calibrator includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the sampler.Type: GrantFiled: June 24, 2021Date of Patent: August 9, 2022Assignee: QUALCOMM IncorporatedInventors: Masoud Moslehi Bajestan, Marco Zanuso, Razak Hossain, Hasnain Lakdawala
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Publication number: 20210409029Abstract: An apparatus implements a multiplying delay-locked loop (MDLL) including a sampler to be calibrated. In an example aspect, an apparatus includes an MDLL and a sampler calibrator. The MDLL includes a locked-loop feedforward path with a sampler, a control output, a feedback input, and a reference input coupled to a reference signal source. The MDLL also includes a VCO, a multiplexer, and a divider. The VCO includes a VCO input, a VCO output, and a control input coupled to the control output. The multiplexer includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the VCO input. The divider is coupled between the VCO output and the feedback input. The sampler calibrator includes a first input coupled to the reference signal source, a second input coupled to the VCO output, and an output coupled to the sampler.Type: ApplicationFiled: June 24, 2021Publication date: December 30, 2021Inventors: Masoud Moslehi Bajestan, Marco Zanuso, Razak Hossain, Hasnain Lakdawala
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Publication number: 20210409007Abstract: An apparatus can implement a frequency doubler with duty cycle correction in conjunction with, for instance, a phase-locked loop (PLL) to decrease phase noise. In an example aspect, an apparatus has a frequency doubler including a signal combiner, a first signal pathway, and a second signal pathway. The frequency doubler also includes a doubler input node and a doubler output node. The signal combiner is coupled to the doubler output node. The first signal pathway is coupled between the doubler input node and the signal combiner and includes a first adjustable delay cell. The second signal pathway is also coupled between the doubler input node and the signal combiner and includes a second adjustable delay cell.Type: ApplicationFiled: June 29, 2021Publication date: December 30, 2021Inventors: Masoud Moslehi Bajestan, Marco Zanuso, Razak Hossain, Hasnain Lakdawala
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Publication number: 20200177126Abstract: Certain aspects provide a circuit for generating an oscillating signal. The circuit generally includes a voltage-controlled oscillator (VCO) having cross-coupled transistors, a first capacitive element and a second capacitive element coupled to the cross-coupled transistors, and a first inductive element and a second inductive element coupled to the cross-coupled transistors. First terminals of the first inductive element and the second inductive element are coupled to first terminals of the first capacitive element and the second capacitive element, respectively. The circuit also includes a control circuit having an output coupled to a supply voltage node at second terminals of the first inductive element and the second inductive element, and a feedback path coupled between the VCO and an input of the control circuit.Type: ApplicationFiled: November 27, 2019Publication date: June 4, 2020Inventors: Gang LIU, Mohammad FARAZIAN, Wu-Hsin CHEN, Razak HOSSAIN
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Patent number: 9032354Abstract: A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.Type: GrantFiled: May 28, 2013Date of Patent: May 12, 2015Assignee: STMicroelectronics, Inc.Inventor: Razak Hossain
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Publication number: 20130262944Abstract: A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.Type: ApplicationFiled: May 28, 2013Publication date: October 3, 2013Applicant: STMicroelectronics, Inc.Inventor: Razak Hossain
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Patent number: 8453098Abstract: A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.Type: GrantFiled: March 30, 2009Date of Patent: May 28, 2013Assignee: STMicroelectronics, Inc.Inventor: Razak Hossain
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Patent number: 8203475Abstract: A parallel, multi-stage noise shaping (MASH) delta-sigma (??) modulator reduces the required operating frequency by predicting the inputs to later stages of a serial MASH modulator to be multiples of the MASH input. An Nth order parallel MASH ?? modulator generates N outputs (one from each stage) in a single modulator cycle. Accordingly, the Nth order parallel MASH ?? modulator may be operated at 1/N the frequency of a corresponding prior art Nth order serial MASH ?? modulator.Type: GrantFiled: May 24, 2010Date of Patent: June 19, 2012Assignee: ST-Ericsson SAInventors: Razak Hossain, Andras Pozsgay
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Publication number: 20110285565Abstract: A parallel, multi-stage noise shaping (MASH) delta-sigma (??) modulator reduces the required operating frequency by predicting the inputs to later stages of a serial MASH modulator to be multiples of the MASH input. An Nth order parallel MASH ?? modulator generates N outputs (one from each stage) in a single modulator cycle. Accordingly, the Nth order parallel MASH ?? modulator may be operated at 1/N the frequency of a corresponding prior art Nth order serial MASH ?? modulator.Type: ApplicationFiled: May 24, 2010Publication date: November 24, 2011Applicant: ST-Ericsson SAInventors: Razak Hossain, Andras Pozsgay
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Patent number: 7571402Abstract: A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.Type: GrantFiled: August 28, 2003Date of Patent: August 4, 2009Assignee: STMicroelectronics, Inc.Inventor: Razak Hossain
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Publication number: 20090193307Abstract: A leakage power control vector is loaded into existing test scan chain elements for application to circuit elements of a circuit in which the leakage currents are to be controlled. The vector is designed to configure the circuit elements into states in which leakage currents are reduced. A multiplexer selects the power control vector for loading into the scan chain elements, and a clock generator clocks the configuration vector into the scan chain elements. A sleep mode detector may be provided to configure the multiplexer to select the power control vector and to operate the clock generator to clock the power control vector into the scan chain elements when a sleep mode of the circuit is detected.Type: ApplicationFiled: March 30, 2009Publication date: July 30, 2009Inventor: Razak Hossain
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Publication number: 20080100367Abstract: In a semiconductor device, a method for reducing the effect of crosstalk from an aggressor line to a victim line begins with sensing the occurrence of a voltage change on the aggressor line that can induce a voltage pulse having a pulse magnitude that exceeds a pulse threshold on the victim line. The induced voltage pulse is counteracted by coupling the victim line to a counteracting voltage source. After a predetermined delay period, the coupling of the counteracting voltage source is removed from the victim line. The voltage change on the aggressor line my be sensed from a node connected to either the aggressor line or the victim line. A rising induced pulse is counteracted by coupling the victim line to a more negative voltage source, and a falling induced pulse is counteracted by coupling the victim line to a more positive voltage source.Type: ApplicationFiled: December 26, 2007Publication date: May 1, 2008Applicant: STMICROELECTRONICS, INC.Inventor: Razak Hossain
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Patent number: 7337419Abstract: In a semiconductor device, a method for reducing the effect of crosstalk from an aggressor line to a victim line begins with sensing the occurrence of a voltage change on the aggressor line that can induce a voltage pulse having a pulse magnitude that exceeds a pulse threshold on the victim line. The induced voltage pulse is counteracted by coupling the victim line to a counteracting voltage source. After a predetermined delay period, the coupling of the counteracting voltage source is removed from the victim line. The voltage change on the aggressor line my be sensed from a node connected to either the aggressor line or the victim line. A rising induced pulse is counteracted by coupling the victim line to a more negative voltage source, and a falling induced pulse is counteracted by coupling the victim line to a more positive voltage source.Type: GrantFiled: July 29, 2004Date of Patent: February 26, 2008Assignee: STMicroelectronics, Inc.Inventor: Razak Hossain
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Patent number: 7301372Abstract: A testable, prechargeable circuit has a driving circuit for producing a driving circuit output signal. A timing circuit receives a clock signal and the driving circuit output signal to cause an output of the testable, prechargeable circuit to be in a low state when the clock signal is low. The timing circuit also causes the output of the circuit to be timed with a state change in the clock signal to provide a domino logic output signal. Either a data signal or a test signal are multiplexed to the input of the driving circuit to produce respectively the domino logic output signal or a test output signal. A static logic circuit receives the test output signal to produce a test signal output.Type: GrantFiled: January 17, 2006Date of Patent: November 27, 2007Assignee: STMicroelectronics, Inc.Inventors: Scott B. Anderson, Razak Hossain, Thomas D. Zounes
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Patent number: 7254796Abstract: A method for synthesizing a domino logic circuit design from a source circuit definition using a static logic circuit synthesis tool includes generating a preliminary domino logic circuit design using the circuit synthesis tool and optimizing an attribute of the preliminary domino logic circuit design by substituting a static cell design for a domino cell design having a same function in the preliminary domino logic circuit design.Type: GrantFiled: August 19, 2005Date of Patent: August 7, 2007Assignee: STMicroelectronics, Inc.Inventors: Razak Hossain, Fabrizio Viglione, Bernard Bourgin
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Publication number: 20060114029Abstract: A testable, prechargeable circuit has a driving circuit for producing a driving circuit output signal. A timing circuit receives a clock signal and the driving circuit output signal to cause an output of the testable, prechargeable circuit to be in a low state when the clock signal is low. The timing circuit also causes the output of the circuit to be timed with a state change in the clock signal to provide a domino logic output signal. Either a data signal or a test signal are multiplexed to the input of the driving circuit to produce respectively the domino logic output signal or a test output signal. A static logic circuit receives the test output signal to produce a test signal output.Type: ApplicationFiled: January 17, 2006Publication date: June 1, 2006Inventors: Scott Anderson, Razak Hossain, Thomas Zounes
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Publication number: 20060039551Abstract: In a semiconductor device, a method for reducing the effect of crosstalk from an aggressor line to a victim line begins with sensing the occurrence of a voltage change on the aggressor line that can induce a voltage pulse having a pulse magnitude that exceeds a pulse threshold on the victim line. The induced voltage pulse is counteracted by coupling the victim line to a counteracting voltage source. After a predetermined delay period, the coupling of the counteracting voltage source is removed from the victim line. The voltage change on the aggressor line my be sensed from a node connected to either the aggressor line or the victim line. A rising induced pulse is counteracted by coupling the victim line to a more negative voltage source, and a falling induced pulse is counteracted by coupling the victim line to a more positive voltage source.Type: ApplicationFiled: July 29, 2004Publication date: February 23, 2006Inventor: Razak Hossain