Patents by Inventor Reed Linde

Reed Linde has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11919046
    Abstract: A method of sorting an electronic device includes receiving first data generated by a test tool that is performing a test operation on the electronic device according to a test program, and a provisional binning assignment for the electronic device determined from the first data. The method also includes defining a permanent binning assignment for the electronic device based at least in part on applying a first algorithm and a second algorithm to the first data, the first algorithm and the second algorithm being different. The method further includes outputting the permanent binning assignment so that after the test operation is completed, the electronic device is removed from the test tool and placed in one of a plurality of bins according to the permanent binning assignment.
    Type: Grant
    Filed: December 22, 2021
    Date of Patent: March 5, 2024
    Assignee: Optimal Plus Ltd.
    Inventors: Reed Linde, Gill Balog
  • Publication number: 20220184665
    Abstract: A method of sorting an electronic device includes receiving first data generated by a test tool that is performing a test operation on the electronic device according to a test program, and a provisional binning assignment for the electronic device determined from the first data. The method also includes defining a permanent binning assignment for the electronic device based at least in part on applying a first algorithm and a second algorithm to the first data, the first algorithm and the second algorithm being different. The method further includes outputting the permanent binning assignment so that after the test operation is completed, the electronic device is removed from the test tool and placed in one of a plurality of bins according to the permanent binning assignment.
    Type: Application
    Filed: December 22, 2021
    Publication date: June 16, 2022
    Applicant: Optimal Plus Ltd.
    Inventors: Reed Linde, Gill Balog
  • Patent number: 11235355
    Abstract: Systems and methods for sorting an electronic device undergoing a final test operation in accordance with a test program, into one of a plurality of bins. In one embodiment, an evaluator defines the binning of the electronic device while the device is still socketed, and the defined binning may or may not concur with the binning assigned by the test program.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: February 1, 2022
    Assignee: Optimal Plus Ltd.
    Inventors: Reed Linde, Gill Balog
  • Publication number: 20190160494
    Abstract: Systems and methods for sorting an electronic device undergoing a final test operation in accordance with a test program, into one of a plurality of bins. In one embodiment, an evaluator defines the binning of the electronic device while the device is still socketed, and the defined binning may or may not concur with the binning assigned by the test program.
    Type: Application
    Filed: October 24, 2018
    Publication date: May 30, 2019
    Inventors: Reed Linde, Gill Balog
  • Patent number: 10118200
    Abstract: Systems and methods for sorting an electronic device undergoing a final test operation in accordance with a test program, into one of a plurality of bins. In one embodiment, an evaluator defines the binning of the electronic device while the device is still socketed, and the defined binning may or may not concur with the binning assigned by the test program.
    Type: Grant
    Filed: July 6, 2009
    Date of Patent: November 6, 2018
    Assignee: OPTIMAL PLUS LTD
    Inventors: Reed Linde, Gil Balog
  • Patent number: 9529036
    Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.
    Type: Grant
    Filed: September 22, 2014
    Date of Patent: December 27, 2016
    Assignee: Optimal Plus Ltd.
    Inventors: Gil Balog, Reed Linde, Avi Golan
  • Publication number: 20160321594
    Abstract: Disclosed are methods, systems and computer program products for concluding whether or not there is a correlation between a set of manufacturing condition(s) and performance of in-field end user devices. Also disclosed are methods, systems and computer program products for concluding whether or not there is an inconsistency in in-field end user devices data and/or manufacturing data associated with electronic elements included in end-user devices. In one example, a method includes analyzing received in-field data and/or data computed based on received in-field data, in order to determine whether or not there is a statistically significant difference in in-field performance between end-user devices including elements from a first population and end-user devices including elements from a second population, where manufacturing of the first population corresponds to a set of one or more manufacturing conditions, but manufacturing of the second population does not correspond to the set.
    Type: Application
    Filed: July 28, 2015
    Publication date: November 3, 2016
    Inventors: Reed LINDE, Michael SCHULDENFREI, Dan GLOTTER, Bruce Alan Phillips
  • Publication number: 20150012237
    Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.
    Type: Application
    Filed: September 22, 2014
    Publication date: January 8, 2015
    Inventors: Gil Balog, Reed Linde, Avi Golan
  • Patent number: 8872538
    Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.
    Type: Grant
    Filed: March 14, 2013
    Date of Patent: October 28, 2014
    Assignee: Optimal Plus Ltd.
    Inventors: Gil Balog, Reed Linde, Avi Golan
  • Patent number: 8838408
    Abstract: Systems and methods for deciding whether or not to indicate misalignment. In some examples, an analysis of parametric data relating to tests sensitive to misalignment is performed in order to determine which data is incongruous and to identify corresponding probes or socket contacts as suspected misaligned. In some examples, additionally or alternatively, a spatial analysis quantifies the placement of a set of identified suspected misaligned probes, which were identified from pass/fail test data and/or parametric test data, with respect to a contiguous or non-contiguous area on one or more wafers.
    Type: Grant
    Filed: November 11, 2010
    Date of Patent: September 16, 2014
    Assignee: Optimal Plus Ltd
    Inventors: Reed Linde, Dan Glotter, Alexander Chufarovsky, Leonid Gurov
  • Patent number: 8781773
    Abstract: Methods, systems, computer-program products and program-storage devices for determining whether or not to perform an action based at least partly on an estimated maximum test-range. One method comprises: attaining results generated from a parametric test on semiconductor devices included in a control set; selecting from the semiconductor devices at least one extreme subset including at least one of a high-scoring subset and a low-scoring subset; plotting at least results of the at least one extreme subset; fitting a plurality of curves to a plurality of subsets of the results; extending the curves to the zero-probability axis for the low-scoring subset or the one-probability axis for the high-scoring subset to define a corresponding plurality of intersection points; defining an estimated maximum test range based on at least one of the intersection points; and determining whether or not to perform an action based at least partly on the estimated maximum test range.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: July 15, 2014
    Assignee: Optimal Plus Ltd
    Inventors: Leonid Gurov, Alexander Chufarovsky, Gil Balog, Reed Linde
  • Patent number: 8421494
    Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.
    Type: Grant
    Filed: May 23, 2011
    Date of Patent: April 16, 2013
    Assignee: OptimalTest Ltd.
    Inventors: Gil Balog, Reed Linde, Avi Golan
  • Publication number: 20120123734
    Abstract: Systems and methods for deciding whether or not to indicate misalignment. In some examples, an analysis of parametric data relating to tests sensitive to misalignment is performed in order to determine which data is incongruous and to identify corresponding probes or socket contacts as suspected misaligned. In some examples, additionally or alternatively, a spatial analysis quantifies the placement of a set of identified suspected misaligned probes, which were identified from pass/fail test data and/or parametric test data, with respect to a contiguous or non-contiguous area on one or more wafers.
    Type: Application
    Filed: November 11, 2010
    Publication date: May 17, 2012
    Applicant: OPTIMALTEST LTD.
    Inventors: Reed LINDE, Dan GLOTTER, Alexander CHUFAROVSKY, Leonid GUROV
  • Publication number: 20110251812
    Abstract: Methods, systems, computer program products and program storage devices for determining whether or not to perform an action based at least partly on an estimated maximum test range.
    Type: Application
    Filed: June 21, 2011
    Publication date: October 13, 2011
    Applicant: OPTIMALTEST LTD.
    Inventors: Leonid GUROV, Alexander CHUFAROVSKY, Gil BALOG, Reed LINDE
  • Publication number: 20110224938
    Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.
    Type: Application
    Filed: May 23, 2011
    Publication date: September 15, 2011
    Applicant: OptimalTest Ltd.
    Inventors: Gil Balog, Reed Linde, Avi Golan
  • Patent number: 7969174
    Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.
    Type: Grant
    Filed: April 3, 2009
    Date of Patent: June 28, 2011
    Assignee: OptimalTest Ltd.
    Inventors: Gil Balog, Reed Linde, Avi Golan
  • Publication number: 20110000829
    Abstract: Systems and methods for sorting an electronic device undergoing a final test operation in accordance with a test program, into one of a plurality of bins. In one embodiment, an evaluator defines the binning of the electronic device while the device is still socketed, and the defined binning may or may not concur with the binning assigned by the test program.
    Type: Application
    Filed: July 6, 2009
    Publication date: January 6, 2011
    Applicant: OptimalTest Ltd.
    Inventors: Reed Linde, Gill Balog
  • Publication number: 20090192754
    Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.
    Type: Application
    Filed: April 3, 2009
    Publication date: July 30, 2009
    Applicant: OptimalTest Ltd.
    Inventors: Gil Balog, Reed Linde, Avi Golan
  • Patent number: 7528622
    Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.
    Type: Grant
    Filed: December 28, 2006
    Date of Patent: May 5, 2009
    Assignee: Optimal Test Ltd.
    Inventors: Gil Balog, Reed Linde, Avi Golan
  • Publication number: 20090013218
    Abstract: Methods, systems and modules for datalog management. In one embodiment, the logging of data is allowed to at least occasionally occur while the handling equipment is preparing device(s) for testing. Additionally or alternatively, in one embodiment with a plurality of test site controllers, after testing has been completed at all test site(s) associated with a particular test site controller the logging of data relating to that test site controller is allowed to at least occasionally occur while testing is continuing at test site(s) associated with other test site controller(s).
    Type: Application
    Filed: July 2, 2007
    Publication date: January 8, 2009
    Applicant: Optimal Test Ltd.
    Inventors: Eran ROUSSEAU, Igal GURVITS, Reed LINDE, Gil BALOG