Patents by Inventor Reed Linde

Reed Linde has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Ultra low pin count interface for die testing
    Patent number: 7405586
    Abstract: An apparatus, a method and a system to test a device. An input/output (I/O) block communicates with an external tester to receive test data and to send test result using first and second communication modes. A logic block parses the test data. A memory stores microcode from the parsed test data. The microcode contains a test program to test a circuit. A controller executes the test program.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: July 29, 2008
    Assignee: Intel Corporation
    Inventors: Sunil Gupta, Reed Linde, Rich Fackenthal
  • Ultra low pin count interface for die testing
    Publication number: 20070216438
    Abstract: An apparatus, a method and a system to test a device. An input/output (I/O) block communicates with an external tester to receive test data and to send test result using first and second communication modes. A logic block parses the test data. A memory stores microcode from the parsed test data. The microcode contains a test program to test a circuit. A controller executes the test program.
    Type: Application
    Filed: March 20, 2006
    Publication date: September 20, 2007
    Inventors: Sunil Gupta, Reed Linde, Rich Fackenthal
  • System and methods for test time outlier detection and correction in integrated circuit testing
    Publication number: 20070132477
    Abstract: Methods and systems for semiconductor testing are disclosed. In one embodiment, devices which are testing too slowly are prevented from completing testing, thereby allowing untested devices to begin testing sooner.
    Type: Application
    Filed: December 28, 2006
    Publication date: June 14, 2007
    Applicant: Optimal Test Ltd.
    Inventors: Gil Balog, Reed Linde, Avi Golan
  • Memory defect detection and self-repair technique
    Patent number: 7177189
    Abstract: According to some embodiments, a memory device having multiple memory units includes one or more redundant memory units. Upon detection of an electrical characteristic indicating a failing memory unit, one of the redundant memory units is used to replace the failing memory unit. Detection of failing memory units may be via current, voltage and/or resistance monitoring. If the electrical characteristic monitored exceeds a predetermined threshold, a memory unit is considered failing. The failing memory unit is removed from further use. The redundant memory unit is programmed to be accessible at the memory address of the removed memory unit. Replacement occurs automatically (that is, without user intervention).
    Type: Grant
    Filed: March 1, 2004
    Date of Patent: February 13, 2007
    Assignee: Intel Corporation
    Inventors: Reed A. Linde, Alec W. Smidt
  • Memory defect detection and self-repair technique
    Publication number: 20050190615
    Abstract: According to some embodiments, a memory device having multiple memory units includes one or more redundant memory units. Upon detection of an electrical characteristic indicating a failing memory unit, one of the redundant memory units is used to replace the failing memory unit. Detection of failing memory units may be via current, voltage and/or resistance monitoring. If the electrical characteristic monitored exceeds a predetermined threshold, a memory unit is considered failing. The failing memory unit is removed from further use. The redundant memory unit is programmed to be accessible at the memory address of the removed memory unit. Replacement occurs automatically (that is, without user intervention).
    Type: Application
    Filed: March 1, 2004
    Publication date: September 1, 2005
    Inventors: Reed Linde, Alec Smidt