Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command to read data from the memory device or a write command to write data to the memory device from a host device, determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists in a hardware module of the plurality of hardware modules, and execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue. The bottleneck release operation includes changing a clock of the hardware module, moving the command to a different hardware module configured to process the command, and combinations thereof.

Abstract: The present disclosure generally relates to ensuring a data storage device consumes as little power as possible. Different HW modules in the data storage device can operate at different frequencies to ensure any bottleneck HW modules operate at as fast a frequency as possible, while non-bottleneck HW modules operate at slower frequencies and hence, consume less power. The frequency for each HW modules is dynamic and is adjusted based upon detected bottlenecks so that the data storage device can operate as efficiently as possible and consume as little power as possible.

Abstract: The present disclosure generally relates to optimizing memory storage performance and power usage. Read operations from flash memory are comprised of a sense operation and a read transfer operation. Usually, these two operations are performed in parallel to achieve high read performance. However, these two operations typically do not take the same amount of time, leading to inefficiencies. By measuring sense busy time, the read transfer clock may be set accordingly so the two operations are equal in time. In so doing, the system will be optimized from both a performance and power consumption point of view.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command to read data from the memory device or a write command to write data to the memory device from a host device, determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists in a hardware module of the plurality of hardware modules, and execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue. The bottleneck release operation includes changing a clock of the hardware module, moving the command to a different hardware module configured to process the command, and combinations thereof.

Abstract: The present disclosure generally relates to ensuring a data storage device consumes as little power as possible. Different HW modules in the data storage device can operate at different frequencies to ensure any bottleneck HW modules operate at as fast a frequency as possible, while non-bottleneck HW modules operate at slower frequencies and hence, consume less power. The frequency for each HW modules is dynamic and is adjusted based upon detected bottlenecks so that the data storage device can operate as efficiently as possible and consume as little power as possible.

Abstract: A data storage device includes a non-volatile memory device that includes at least a first wordline having first data and a second wordline sequential and adjacent to the first wordline and a controller coupled to the non-volatile memory device. The controller is configured to receive a write command to program second data to the second wordline, read and store the first data from the first wordline a in a first location prior to programming the second data, program the second data to the second wordline, re-read and store the first data from the first wordline in a second location during the programming, compare the read first data and the re-read first data, and mark one or more bits of the first wordline that are different based on the comparing. The marked one or more bits are used as soft bits in future read and decode operations.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command to read data from the memory device or a write command to write data to the memory device from a host device, determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists in an input queue corresponding to a hardware module of a plurality of hardware modules, and execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue. The bottleneck release operation includes changing a clock of the hardware module, moving the command to a different hardware module configured to process the command, and combinations thereof.

Abstract: The present disclosure generally relates to improved event filtering, debugging, and flow communication through a flow identifier. Rather than sending messages or events with no identity or with local identity (that is identity that has meaning only to a few modules, and not to all the modules), this disclosure suggests adding a flow identifier to each message or event. The flow identifier is at least two bits added to each message to be later identified when needed. A first message is sent to a HW or FW module. At either the HW or FW module an event will be generated. When the event is generated the flow identifier will be added to the event. The HW or FW module will then send the generated events along with the flow identifier to the TBRAM. Once received, the TBRAM will send the events along with the flow identifier to a PC.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. When a boot operation of the data storage device is initiated, the controller retrieves a relevant boot file from the memory device to boot the data storage device with. The relevant boot file to be retrieved from a plurality of boot files may be determined by a write temperature corresponding to the temperature of when the boot file was programmed to the memory device and a read temperature of the boot file during the boot operation. Each boot file of the plurality of boot files is programmed using different programming parameters in order to cover a range of possible retention levels.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command to read data from the memory device or a write command to write data to the memory device from a host device, determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists either in an input queue corresponding to a hardware module of a plurality of hardware modules or in the hardware module of the plurality of hardware modules, and execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue or in the hardware module.

Abstract: The present disclosure generally relates to improved command processing by separating all state machines into multiple groups. Rather than having one general die that can process any command, this disclosure suggests distributed processing commands by having two types of dies. A slave die will contain the flash array and implementation of state machine that is related to fast operations, and will not include state machines of slow operations. A master die will contain implementation of fast state machine (to support fast commands to the flash array that connected to the master die) and implementation of slow command state machine. The master die will have one instance of the slow state machine implementation, but that slow state machine will be able to be loaded with variables that represent the slow states of all the other dies. The commands processing is based the most suitable state machine for the specific command.

Abstract: The present disclosure generally relates to optimizing memory storage performance and power usage. Read operations from flash memory are comprised of a sense operation and a read transfer operation. Usually, these two operations are performed in parallel to achieve high read performance. However, these two operations typically do not take the same amount of time, leading to inefficiencies. By measuring sense busy time, the read transfer clock may be set accordingly so the two operations are equal in time. In so doing, the system will be optimized from both a performance and power consumption point of view.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command to read data from the memory device or a write command to write data to the memory device from a host device, determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists in an input queue corresponding to a hardware module of a plurality of hardware modules, and execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue. The bottleneck release operation includes changing a clock of the hardware module, moving the command to a different hardware module configured to process the command, and combinations thereof.

Abstract: The present disclosure generally relates to improved event filtering, debugging, and flow communication through a flow identifier. Rather than sending messages or events with no identity or with local identity (that is identity that has meaning only to a few modules, and not to all the modules), this disclosure suggests adding a flow identifier to each message or event. The flow identifier is at least two bits added to each message to be later identified when needed. A first message is sent to a HW or FW module. At either the HW or FW module an event will be generated. When the event is generated the flow identifier will be added to the event. The HW or FW module will then send the generated events along with the flow identifier to the TBRAM. Once received, the TBRAM will send the events along with the flow identifier to a PC.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command to read data from the memory device or a write command to write data to the memory device from a host device, determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists in a hardware module of the plurality of hardware modules, and execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue. The bottleneck release operation includes changing a clock of the hardware module, moving the command to a different hardware module configured to process the command, and combinations thereof.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive a read command to read data from the memory device or a write command to write data to the memory device from a host device, determine whether a bottleneck exists in a data/control path between the host device and the memory device, wherein the bottleneck exists either in an input queue corresponding to a hardware module of a plurality of hardware modules or in the hardware module of the plurality of hardware modules, and execute a bottleneck release operation when the bottleneck exists in the data/control path between the host device and the memory device, wherein the bottleneck release operation is dependent on whether the bottleneck exists in the input queue or in the hardware module.

Abstract: A data storage device includes a non-volatile memory device that includes at least a first wordline having first data and a second wordline sequential and adjacent to the first wordline and a controller coupled to the non-volatile memory device. The controller is configured to receive a write command to program second data to the second wordline, read and store the first data from the first wordline a in a first location prior to programming the second data, program the second data to the second wordline, re-read and store the first data from the first wordline in a second location during the programming, compare the read first data and the re-read first data, and mark one or more bits of the first wordline that are different based on the comparing. The marked one or more bits are used as soft bits in future read and decode operations.

Abstract: The present disclosure generally relates to ensuring a data storage device consumes as little power as possible. Different HW modules in the data storage device can operate at different frequencies to ensure any bottleneck HW modules operate at as fast a frequency as possible, while non-bottleneck HW modules operate at slower frequencies and hence, consume less power. The frequency for each HW modules is dynamic and is adjusted based upon detected bottlenecks so that the data storage device can operate as efficiently as possible and consume as little power as possible.

Abstract: A data storage device includes a memory device and a controller coupled to the memory device. The controller is configured to receive read requests from a host device. When a read request is received corresponding to one or more pages from a first plane and one or more pages from a second plane, the controller is configured to determine a decode time for the pages of the first plane and the pages of the second plane. Based on the decode times for pages of the first plane and pages of the second page, pages of the first plane that have a similar decode time to pages of the second plane are read in parallel.

Abstract: The present disclosure generally relates to improving data transfer speed. A data storage device includes both a controller and a memory device. The controller provides instructions regarding read and/or write commands to the memory device through the use of control lines. The data to be written/read is transferred between the controller and the memory device along data lines. The control lines typically are not used during data transfer. During data transfer, the control lines can be used to increase data transfer speed by utilizing the otherwise idle control lines for data transfer in addition to the data lines. Hence, data transfer speed is increased by using not only the data lines, but additionally the control lines. Once the data transfer is complete, the control lines return to their legacy function.