Patents by Inventor Regina Freed
Regina Freed has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10600688Abstract: Methods and apparatus to form fully self-aligned vias are described. A seed gapfill layer is formed on a recessed first insulating layers positioned between first conductive lines. Pillars are formed from the seed gapfill layer and a second insulating layer is deposited in the gaps between pillars. The pillars are removed and a third insulating layer is deposited in the gaps in the second insulating layer to form an overburden of third insulating layer. A portion of the overburden of the third insulating layer is removed to expose the first conductive lines and form vias.Type: GrantFiled: August 29, 2018Date of Patent: March 24, 2020Assignee: Micromaterials LLCInventors: Ying Zhang, Regina Freed, Nitin K. Ingle, Ho-yung David Hwang, Uday Mitra
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Patent number: 10593594Abstract: Methods of forming a self-aligned via comprising recessing a first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is formed on the first insulating layer. A via is formed through the second insulating layer to one of the first conductive lines. Semiconductor devices comprising the self-aligned via and apparatus for forming the self-aligned via are also disclosed.Type: GrantFiled: December 11, 2018Date of Patent: March 17, 2020Assignee: Micromaterials LLCInventors: Yung-Chen Lin, Qingjun Zhou, Ying Zhang, Ho-yung David Hwang, Uday Mitra, Regina Freed
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Patent number: 10573555Abstract: Methods and apparatus to form fully self-aligned vias are described. Portions of first conductive lines are recessed in a first insulating layer on a substrate. A first metal film is formed in the recessed portions of the first conductive lines and pillars are formed from the first metal film. A second insulating layer is deposited around the pillars. The pillars are removed to form vias in the second insulating layer. A third insulating layer is deposited in the vias and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer. The third insulating layer is etched from the filled vias to form a via opening to the first conductive line.Type: GrantFiled: August 29, 2018Date of Patent: February 25, 2020Assignee: Micromaterials LLCInventors: Ying Zhang, Regina Freed, Nitin K. Ingle, Ho-yung Hwang, Uday Mitra, Abhijit Basu Mallick
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Patent number: 10553485Abstract: Methods and apparatus to form fully self-aligned vias are described. First conductive lines are recessed in a first insulating layer on a substrate. A first metal film is formed in the recessed first conductive lines and pillars are formed from the first metal film. Some of the pillars are selectively removed and a second insulating layer is deposited around the remaining pillar. The remaining pillars are removed to form vias in the second insulating layer. A third insulating layer is deposited in the vias and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer. The third insulating layer is etched from the filled vias to form a via opening to the first conductive line.Type: GrantFiled: June 22, 2018Date of Patent: February 4, 2020Assignee: Micromaterials LLCInventors: Ying Zhang, Regina Freed, Nitin K. Ingle, Ho-yung Hwang, Uday Mitra, Abhijit Basu Mallick, Sanjay Natarajan
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Patent number: 10522404Abstract: A first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is on the first insulating layer. A second metallization layer comprises a set of second conductive lines on a third insulating layer and on the second insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. A via between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines.Type: GrantFiled: July 24, 2019Date of Patent: December 31, 2019Assignee: Micromaterials LLCInventors: Ying Zhang, Abhijit Basu Mallick, Regina Freed, Nitin K. Ingle, Uday Mitra, Ho-yung Hwang
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Publication number: 20190378756Abstract: Apparatuses and methods to provide a fully self-aligned via are described. Some embodiments of the disclosure provide an electronic device having a liner that is selectively removable when compared to conductive lines. The liner may be selectively removed by utilizing one or more of a base (e.g. sodium hydroxide) and hydrogen peroxide.Type: ApplicationFiled: May 29, 2019Publication date: December 12, 2019Inventors: Amrita B. Mullick, Nitin K. Ingle, Xikun Wang, Regina Freed, Uday Mitra, Ho-yung David Hwang
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Publication number: 20190355620Abstract: Apparatuses and methods to provide a fully self-aligned via are described. Some embodiments of the disclosure provide an electronic device having a bridging via between a first metallization and a third metallization layer, the bridging via not contacting a second metallization layers. Methods of providing self-aligned bridging vias are also described.Type: ApplicationFiled: May 14, 2019Publication date: November 21, 2019Inventors: Regina Freed, Uday Mitra, Sanjay Natarajan
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Publication number: 20190348322Abstract: Apparatuses and methods to provide a fully self-aligned via are described. Some embodiments of the disclosure utilize a cap layer to protect an insulating layer in order to minimize bowing of the side walls during metal recess in a fully self-aligned via. The cap layer can be selectively removed, thus increasing the aspect ratio, by exposing the substrate to a hot phosphoric acid solution.Type: ApplicationFiled: May 6, 2019Publication date: November 14, 2019Inventors: Amrita B. Mullick, Madhur Sachan, He Ren, Swaminathan Srinivasan, Regina Freed, Uday Mitra
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Publication number: 20190348323Abstract: A first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is on the first insulating layer. A second metallization layer comprises a set of second conductive lines on a third insulating layer and on the second insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. A via between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines.Type: ApplicationFiled: July 24, 2019Publication date: November 14, 2019Inventors: Ying Zhang, Abhijit Basu Mallick, Regina Freed, Nitin K. Ingle, Uday Mitra, Ho-yung Hwang
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Patent number: 10424507Abstract: A first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is on the first insulating layer. A second metallization layer comprises a set of second conductive lines on a third insulating layer and on the second insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. A via between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines.Type: GrantFiled: August 17, 2017Date of Patent: September 24, 2019Assignee: Mirocmaterials LLCInventors: Ying Zhang, Abhijit Basu Mallick, Regina Freed, Nitin K. Ingle, Uday Mitra, Ho-yung Hwang
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Patent number: 10410921Abstract: A first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is on the first insulating layer. A second metallization layer comprises a set of second conductive lines on a third insulating layer and on the second insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. A via between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines.Type: GrantFiled: February 11, 2019Date of Patent: September 10, 2019Assignee: Micromaterials LLCInventors: Ying Zhang, Abhijit Basu Mallick, Regina Freed, Nitin K. Ingle, Uday Mitra, Ho-yung David Hwang
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Publication number: 20190273019Abstract: Methods to remove metal oxides from substrate surfaces are described. Some embodiments of the disclosure utilize an aqueous alkaline solution to remove metal oxides from substrate surfaces using a wet method. Some embodiments of the disclosure are performed at atmospheric pressure and lower temperatures. Methods of forming self-aligned vias are also described.Type: ApplicationFiled: March 1, 2019Publication date: September 5, 2019Inventors: Amrita B. Mullick, Uday Mitra, Regina Freed
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Publication number: 20190198392Abstract: Methods of etching tungsten are disclosed including: leveling a first top surface of a tungsten layer within a feature and atop a top surface of a substrate; and etching the tungsten layer with a peroxide such as hydrogen peroxide and one of a strong acid or a strong base to remove a first portion of the tungsten layer from atop the substrate to form a second top surface of a tungsten layer at a level below the top surface of the substrate. The methods are suitable for forming substantially level or flat top surfaces of a tungsten layer at a level below the top surface of the substrate or within one or more features such as vias or trenches.Type: ApplicationFiled: December 22, 2017Publication date: June 27, 2019Inventors: AMRITA B. MULLICK, ISMAIL EMESH, UDAY MITRA, ROEY SHAVIV, REGINA FREED
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Publication number: 20190198389Abstract: Methods of etching a metal layer and a metal-containing barrier layer to a predetermined depth are described. In some embodiments, the metal layer and metal-containing barrier layer are formed on a substrate with a first dielectric and a second dielectric thereon. The metal layer and the metal-containing barrier layer formed within a feature in the first dielectric and the second dielectric. In some embodiments, the metal layer and metal-containing barrier layer can be sequentially etched from a feature formed in a dielectric material. In some embodiments, the sidewalls of the feature formed in a dielectric material are passivated to change the adhesion properties of the dielectric material.Type: ApplicationFiled: December 10, 2018Publication date: June 27, 2019Inventors: He Ren, Amrita B. Mullick, Regina Freed, Mehul Naik, Uday Mitra
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Publication number: 20190189510Abstract: Methods of forming a self-aligned via comprising recessing a first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is formed on the first insulating layer. A via is formed through the second insulating layer to one of the first conductive lines. Semiconductor devices comprising the self-aligned via and apparatus for forming the self-aligned via are also disclosed.Type: ApplicationFiled: December 11, 2018Publication date: June 20, 2019Inventors: Yung-Chen Lin, Qingjun Zhou, Ying Zhang, Ho-yung David Hwang, Uday Mitra, Regina Freed
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Publication number: 20190189512Abstract: A first metallization layer comprising a set of first conductive lines that extend along a first direction on a first insulating layer on a substrate. A second insulating layer is on the first insulating layer. A second metallization layer comprises a set of second conductive lines on a third insulating layer and on the second insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. A via between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines.Type: ApplicationFiled: February 11, 2019Publication date: June 20, 2019Inventors: Ying Zhang, Abhijit Basu Mallick, Regina Freed, Nitin K. Ingle, Uday Mitra, Ho-yung David Hwang
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Publication number: 20190189456Abstract: Processing methods to etch metal oxide films with less etch residue are described. The methods comprise etching a metal oxide film with a metal halide etchant, and exposing the etch residue to a reductant to remove the etch residue. Some embodiments relate to etching tungsten oxide films. Some embodiments utilize tungsten halides to etch metal oxide films. Some embodiments utilize hydrogen gas as a reductant to remove etch residues.Type: ApplicationFiled: December 13, 2018Publication date: June 20, 2019Inventors: Amrita B. Mullick, Abhijit Basu Mallick, Srinivas Gandikota, Susmit Singha Roy, Yingli Rao, Regina Freed, Uday Mitra
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Publication number: 20190074219Abstract: Methods and apparatus to form fully self-aligned vias are described. A seed gapfill layer is formed on a recessed first insulating layers positioned between first conductive lines. Pillars are formed from the seed gapfill layer and a second insulating layer is deposited in the gaps between pillars. The pillars are removed and a third insulating layer is deposited in the gaps in the second insulating layer to form an overburden of third insulating layer. A portion of the overburden of the third insulating layer is removed to expose the first conductive lines and form vias.Type: ApplicationFiled: August 29, 2018Publication date: March 7, 2019Inventors: Ying Zhang, Regina Freed, Nitin K. Ingle, Ho-yung Hwang, Uday Mitra
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Publication number: 20190067103Abstract: Methods and apparatus to form fully self-aligned vias are described. Portions of first conductive lines are recessed in a first insulating layer on a substrate. A first metal film is formed in the recessed portions of the first conductive lines and pillars are formed from the first metal film. A second insulating layer is deposited around the pillars. The pillars are removed to form vias in the second insulating layer. A third insulating layer is deposited in the vias and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer. The third insulating layer is etched from the filled vias to form a via opening to the first conductive line.Type: ApplicationFiled: August 29, 2018Publication date: February 28, 2019Inventors: Ying Zhang, Regina Freed, Nitin K. Ingle, Ho-yung Hwang, Uday Mitra, Abhijit Basu Mallick
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Publication number: 20180374750Abstract: Methods and apparatus to form fully self-aligned vias are described. First conductive lines are recessed in a first insulating layer on a substrate. A first metal film is formed in the recessed first conductive lines and pillars are formed from the first metal film. Some of the pillars are selectively removed and a second insulating layer is deposited around the remaining pillar. The remaining pillars are removed to form vias in the second insulating layer. A third insulating layer is deposited in the vias and an overburden is formed on the second insulating layer. Portions of the overburden are selectively etched from the second insulating layer to expose the second insulating layer and the filled vias and leaving portions of the third insulating layer on the second insulating layer. The third insulating layer is etched from the filled vias to form a via opening to the first conductive line.Type: ApplicationFiled: June 22, 2018Publication date: December 27, 2018Inventors: Ying Zhang, Regina Freed, Nitin K. Ingle, Ho-yung Hwang, Uday Mitra, Abhijit Basu Mallick, Sanjay Natarajan