Patents by Inventor Reiji Niino

Reiji Niino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9162252
    Abstract: According to an embodiment of the present disclosure, a method of forming a polyimide film on a substrate is disclosed. Such method can be easily controlled and form a polyimide film applicable as an insulation film. While a wafer is heated at a temperature at which a polyimide film is formed, a cycle, in which the wafer is sequentially supplied with a first processing gas, for example, containing a PMDA-based first monomer, and a second processing gas containing a non-aromatic monomer, for example, an HMDA-based second monomer, is performed for a predetermined number of times. When the processing gases are switched, a replacement gas is supplied into a reaction tube so that the monomers are not mixed together under the atmosphere in the reaction tube.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: October 20, 2015
    Assignee: TOKYO ELECTRON LIMITED
    Inventors: Tatsuya Yamaguchi, Reiji Niino
  • Patent number: 8778815
    Abstract: A method of forming a polyimide film on a surface of a substrate by dehydration condensation of a first monomer including a bifunctional acid anhydride and a second monomer including a bifunctional amine is disclosed. The method includes loading the substrate into a processing chamber, heating the substrate at a temperature at which a polyimide film is formed, and performing a cycle a predetermined number of times. The cycle comprises supplying a first processing gas containing the first monomer to the substrate, supplying a second processing gas containing the second monomer to the substrate. The method further includes supplying a replacement gas in the processing chamber between supplying the first processing gas and supplying the second processing gas thereby replacing atmosphere in the processing chamber by the replacement gas, and evacuating the first and/or the second processing gas out of the processing chamber.
    Type: Grant
    Filed: May 24, 2013
    Date of Patent: July 15, 2014
    Assignee: Tokyo Electron Limited
    Inventors: Tatsuya Yamaguchi, Reiji Niino
  • Publication number: 20130316080
    Abstract: According to an embodiment of the present disclosure, a method of forming a polyimide film on a substrate is disclosed. Such method can be easily controlled and form a polyimide film applicable as an insulation film. While a wafer is heated at a temperature at which a polyimide film is formed, a cycle, in which the wafer is sequentially supplied with a first processing gas, for example, containing a PMDA-based first monomer, and a second processing gas containing a non-aromatic monomer, for example, an HMDA-based second monomer, is performed for a predetermined number of times. When the processing gases are switched, a replacement gas is supplied into a reaction tube so that the monomers are not mixed together under the atmosphere in the reaction tube.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 28, 2013
    Inventors: Tatsuya YAMAGUCHI, Reiji NIINO
  • Publication number: 20130316545
    Abstract: A method of forming a polyimide film on a surface of a substrate by dehydration condensation of a first monomer including a bifunctional acid anhydride and a second monomer including a bifunctional amine is disclosed. The method includes loading the substrate into a processing chamber, heating the substrate at a temperature at which a polyimide film is formed, and performing a cycle a predetermined number of times. The cycle comprises supplying a first processing gas containing the first monomer to the substrate, supplying a second processing gas containing the second monomer to the substrate. The method further includes supplying a replacement gas in the processing chamber between supplying the first processing gas and supplying the second processing gas thereby replacing atmosphere in the processing chamber by the replacement gas, and evacuating the first and/or the second processing gas out of the processing chamber.
    Type: Application
    Filed: May 24, 2013
    Publication date: November 28, 2013
    Inventors: Tatsuya YAMAGUCHI, Reiji NIINO
  • Patent number: 8383522
    Abstract: There is provided a micro pattern forming method including forming a thin film on a substrate; forming a film serving as a mask when processing the thin film; processing the film serving as a mask into a pattern including lines having a preset pitch; trimming the pattern including the lines; and forming an oxide film on the pattern including the lines and on the thin film by alternately supplying a source gas and an activated oxygen species. Here, the process of trimming the pattern and the process of forming an oxide film are consecutively performed in a film forming apparatus configured to form the oxide film.
    Type: Grant
    Filed: June 7, 2011
    Date of Patent: February 26, 2013
    Assignee: Tokyo Electron Limited
    Inventors: Shigeru Nakajima, Kazuhide Hasebe, Pao-Hwa Chou, Mitsuaki Iwashita, Reiji Niino
  • Patent number: 8168375
    Abstract: Disclosed is a patterning method including: forming a first film on a substrate; forming a multi-layered film including a resist film on the first film; forming a patterned resist film having a preset pattern by patterning the resist film by photolithography; forming a silicon oxide film different from the first film on the patterned resist film and the first film by alternately supplying a first gas containing organic silicon and a second gas containing an activated oxygen species to the substrate; etching the silicon oxide film to thereby form a sidewall spacer on a sidewall of the patterned resist film; removing the patterned resist film; and processing the first film by using the sidewall spacer as a mask.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: May 1, 2012
    Assignee: Tokyo Electron Limited
    Inventors: Shigeru Nakajima, Kazuhide Hasebe, Pao-Hwa Chou, Mitsuaki Iwashita, Reiji Niino
  • Publication number: 20110237082
    Abstract: There is provided a micro pattern forming method including forming a thin film on a substrate; forming a film serving as a mask when processing the thin film; processing the film serving as a mask into a pattern including lines having a preset pitch; trimming the pattern including the lines; and forming an oxide film on the pattern including the lines and on the thin film by alternately supplying a source gas and an activated oxygen species. Here, the process of trimming the pattern and the process of forming an oxide film are consecutively performed in a film forming apparatus configured to form the oxide film.
    Type: Application
    Filed: June 7, 2011
    Publication date: September 29, 2011
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Shigeru Nakajima, Kazuhide Hasebe, Pao-Hwa Chou, Mitsuaki Iwashita, Reiji Niino
  • Patent number: 7989354
    Abstract: Disclosed is a patterning method including: forming a first film on a substrate; forming a first resist film on the first film; processing the first resist film into a first resist pattern having a preset pitch by photolithography; forming a silicon oxide film on the first resist pattern and the first film by alternately supplying a first gas containing organic silicon and a second gas containing an activated oxygen species to the substrate; forming a second resist film on the silicon oxide film; processing the second resist film into a second resist pattern having a preset pitch by the photolithography; and processing the first film by using the first resist pattern and the second resist pattern as a mask.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: August 2, 2011
    Assignee: Tokyo Electron Limited
    Inventors: Shigeru Nakajima, Kazuhide Hasebe, Pao-Hwa Chou, Mitsuaki Iwashita, Reiji Niino
  • Patent number: 7754622
    Abstract: Disclosed is a patterning method including: forming, on a thin film, a sacrificial film made of a material different from that of the thin film and made of SiBN; processing the sacrificial film into a pattern having a preset interval by using a photolithography technique; forming, on sidewalls of the processed sacrificial film, sidewall spacers made of a material different from those of the sacrificial film and the thin film; removing the processed sacrificial film; and processing the thin film by using the sidewall spacers as a mask.
    Type: Grant
    Filed: June 6, 2008
    Date of Patent: July 13, 2010
    Assignee: Tokyo Electron Limited
    Inventors: Pao-Hwa Chou, Kazuhide Hasebe, Shigeru Nakajima, Yasushi Akasaka, Mitsuaki Iwashita, Reiji Niino
  • Publication number: 20100130015
    Abstract: Disclosed is a patterning method including: forming a first film on a substrate; forming a first resist film on the first film; processing the first resist film into a first resist pattern having a preset pitch by photolithography; forming a silicon oxide film on the first resist pattern and the first film by alternately supplying a first gas containing organic silicon and a second gas containing an activated oxygen species to the substrate; forming a second resist film on the silicon oxide film; processing the second resist film into a second resist pattern having a preset pitch by the photolithography; and processing the first film by using the first resist pattern and the second resist pattern as a mask.
    Type: Application
    Filed: June 6, 2008
    Publication date: May 27, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Shigeru Nakajima, Kazuhide Hasebe, Pao-Hwa Chou, Mitsuaki Iwashita, Reiji Niino
  • Publication number: 20100112796
    Abstract: Disclosed is a patterning method including: forming, on a thin film, a sacrificial film made of a material different from that of the thin film and made of SiBN; processing the sacrificial film into a pattern having a preset interval by using a photolithography technique; forming, on sidewalls of the processed sacrificial film, sidewall spacers made of a material different from those of the sacrificial film and the thin film; removing the processed sacrificial film; and processing the thin film by using the sidewall spacers as a mask.
    Type: Application
    Filed: June 6, 2008
    Publication date: May 6, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Pao-Hwa Chou, Kazuhide Hasebe, Shigeru Nakajima, Yasushi Akasaka, Mitsuaki Iwashita, Reiji Niino
  • Publication number: 20100112496
    Abstract: A patterning method comprises a step for forming a first film on a substrate, a step for forming a multilayer film including a resist film on the first film, a step for patterning the resist film by photolithography to form a patterned resist film having a predetermined pattern, a step for forming an silicon oxide film different from the first film on the patterned resist film and the first film by supplying a first gas containing an organic silicon and a second gas containing an activated oxygen species alternately to the substrate, a step for etching the silicon oxide film to form a sidewall spacer on the sidewall of the patterned resist film, a step for removing the patterned resist film, and a step for processing the first film by using the sidewall spacer as a mask.
    Type: Application
    Filed: June 6, 2008
    Publication date: May 6, 2010
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Shigeru Nakajima, Kazuhide Hasebe, Pao-Hwa Chou, Mitsuaki Iwashita, Reiji Niino
  • Publication number: 20090311634
    Abstract: A method of patterning a thin film on a substrate is described. The method includes forming a sacrificial structure over the thin film, and forming a photo-resist layer over the sacrificial structure. The sacrificial structure has anti-reflective properties, comprises silicon and is capable of withstanding the photo-resist layer removal process and the stress induced during the spacer layer deposition. Thereafter, an image pattern is formed in one or both of the sacrificial structure or the photo-resist layer. A spacer layer is then conformally deposited over the pattern. The spacer layer is etched back to remove horizontal portions while substantially leaving vertical portions. The remaining photo-resist and/or sacrificial structure that is not overlaid with the etched-back spacer layer is removed leaving spacers that are utilized to transfer another pattern to the thin film.
    Type: Application
    Filed: June 11, 2008
    Publication date: December 17, 2009
    Applicant: TOKYO ELECTRON LIMITED
    Inventors: Hongyu Yue, Hieu A. Lam, Reiji Niino
  • Patent number: 5637153
    Abstract: After a polysilicon film is formed on a wafer, a cleaning gas containing ClF.sub.3 at 10 to 50 vol % is supplied into a reaction tube and an exhaust pipe system at a flow rate of 3000 to 3500 SCCM, so as to remove a polysilicon-based film deposited on an inner wall surface of the reaction tube, the surface of a member incorporated in the reaction tube, and an inner wall surface of the exhaust pipe system while the film forming process, by etching using ClF.sub.3. The cleaning gas is supplied while the temperature in the reaction tube is maintained at 450.degree. C. or higher, and in a pressure condition set at the maintained temperature such that an etching rate of the polysilicon-based film by the cleaning gas is higher than an etching rate of silicon which is the material of the reaction tube or the member incorporated in the reaction tube.
    Type: Grant
    Filed: April 26, 1995
    Date of Patent: June 10, 1997
    Assignee: Tokyo Electron Limited
    Inventors: Reiji Niino, Yoshiyuki Fujita, Hideki Lee, Yasuo Imamura, Toshiharu Nishimura, Yuuichi Mikata, Shinji Miyazaki, Takahiko Moriya, Katsuya Okumura, Hitoshi Kato
  • Patent number: 5500388
    Abstract: In order to form a film on a surface of a semiconductor wafer, a multiplicity of wafers are individually mounted on ring-shaped mounts of a wafer boat, while the temperature within a reaction tube is set at, e.g., 400.degree. C. under a nitrogen gas atmosphere. After loading the wafer boat into the reaction tube, the temperature within the reaction tube is raised up to, e.g., 620.degree. C. at a rate of, e.g., 100.degree. C./min, and SiH.sub.4 gas is supplied onto the surface of a silicon substrate to form a polysilicon film. After film formation, air is forced to flow along the internal surface of the heating section to forcibly cool the interior of the reaction tube. In the case of forming a metal silicon film using a wafer having a silicon substrate and a metal film formed on the surface of the silicon substrate, the temperature within the reaction tube is set at, e.g. 100.degree. C. for loading the wafers.
    Type: Grant
    Filed: February 28, 1994
    Date of Patent: March 19, 1996
    Assignees: Tokyo Electron Kabushiki Kaisha, Tokyo Electron Tohoku Kabushiki Kaisha
    Inventors: Reiji Niino, Tomoyuki Ohbu, Hiroaki Ikegawa, Ken Nakao, Yoshiyuki Fujita, Tsutomu Haraoka, Makoto Kobayashi, Naoya Kaneda, Hiroshi Kumada
  • Patent number: 5380370
    Abstract: Prior to formation of a polysilicon film on a wafer, a pre-coat film having a thickness of 1 .mu.m and consisting of polysilicon is formed on the inner wall surface of a reaction tube or the surface of a member incorporated in the reaction tube. A polysilicon film is formed on the wafer at a temperature of 450.degree. C. to 650.degree. C. A cleaning gas containing ClF.sub.3 having a concentration of 10 to 50 vol. % is supplied into the reaction tube at a flow rate to an area of an object be cleaned of 750 to 3,500 SCCM/m.sup.2 to remove a polysilicon film deposited on the inner wall surface of the reaction tube or the surface of the member incorporated in the reaction tube by etching using the ClF.sub.3. In this case, the cleaning gas is supplied while a temperature in the reaction tube is kept at a temperature of 450.degree. C. to 650.degree. C.
    Type: Grant
    Filed: April 30, 1993
    Date of Patent: January 10, 1995
    Assignee: Tokyo Electron Limited
    Inventors: Reiji Niino, Yoshiyuki Fujita, Hideki Lee, Yasuo Imamura, Toshiharu Nishimura, Yuuichi Mikata, Shinji Miyazaki, Takahiko Moriya, Katsuya Okumura
  • Patent number: 5316472
    Abstract: A semiconductor wafer boat used in a vertical CVD apparatus includes four columns fixed to upper and lower support plates. Each of the columns has a plurality of first grooves arranged at regular intervals in the vertical direction so as to place wafers in substantially parallel to each other, and a plurality of second grooves formed alternately with the first grooves. A plate ring is provided for each of the second grooves so as to improve the uniformity of thickness of a film to be formed on each wafer. Each ring has an outer diameter larger than that of a wafer, and an inner diameter smaller than that of the wafer. Each ring is placed such that there is a clearance for transferring each wafer between each ring and each wafer in the vertical direction.
    Type: Grant
    Filed: December 16, 1992
    Date of Patent: May 31, 1994
    Assignees: Tokyo Electron Limited, Tokyo Electron Sagami Limited, Kabushiki Kaisha Toshiba
    Inventors: Reiji Niino, Isao Siratani, Yutaka Simada, Hiroki Fukusima, Hirofumi Kitayama, Akimichi Yonekura, Yuuichi Mikata
  • Patent number: 5252133
    Abstract: A vertically oriented CVD apparatus comprises a reaction chamber, a boat means vertically placed in the reaction chamber to horizontally support a plurality of semiconductor substrates, and a gas inlet tube including a plurality of gas injection holes along a longitudinal axis thereof and extending along a longitudinal side of the boat means to introduce a reaction gas into the reaction chamber. In the structure, a direction of each of the gas injection holes is set at an angle .theta. with respect to a reference line given by a straight line connecting a center of the gas inlet tube to a center of one of the semiconductor wafers, the angle .theta. being defined by 0.degree. < .theta. .ltoreq. 90.degree..
    Type: Grant
    Filed: December 18, 1991
    Date of Patent: October 12, 1993
    Assignees: Kabushiki Kaisha Toshiba, Tokyo Electron Limited
    Inventors: Shinji Miyazaki, Yuichi Mikata, Takahiko Moriya, Reiji Niino, Motohiko Nishimura