Patents by Inventor Reiko KOMIYA
Reiko KOMIYA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210249440Abstract: A memory device includes a conductive layer, a plurality of first electrode layers, a first semiconductor layer extending through the plurality of first electrode layers in a first direction toward the plurality of first electrode layers from the conductive layer, a first insulating film including a tunneling insulator film, a charge-trapping film and a blocking insulator film, a second electrode layer, and a semiconductor base. The charge-trapping film is spaced along the first direction from the semiconductor base, a distance in the first direction between the charge-trapping film and the semiconductor base is larger than a thickness of the blocking insulator film in a second direction toward the plurality of first electrode layers from the first semiconductor layer.Type: ApplicationFiled: April 28, 2021Publication date: August 12, 2021Applicant: TOSHIBA MEMORY CORPORATIONInventors: Reiko KOMIYA, Tatsuo IZUMI, Takaya YAMANAKA, Takeshi NAGATOMO, Karin TAKAGI
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Patent number: 11024646Abstract: A memory device includes a conductive layer, a plurality of first electrode layers, a first semiconductor layer extending through the plurality of first electrode layers in a first direction toward the plurality of first electrode layers from the conductive layer, a first insulating film including a tunneling insulator film, a charge-trapping film and a blocking insulator film, a second electrode layer, and a semiconductor base. The charge-trapping film is spaced along the first direction from the semiconductor base, a distance in the first direction between the charge-trapping film and the semiconductor base is larger than a thickness of the blocking insulator film in a second direction toward the plurality of first electrode layers from the first semiconductor layer.Type: GrantFiled: November 26, 2019Date of Patent: June 1, 2021Assignee: TOSHIBA MEMORY CORPORATIONInventors: Reiko Komiya, Tatsuo Izumi, Takaya Yamanaka, Takeshi Nagatomo, Karin Takagi
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Publication number: 20200098790Abstract: A memory device includes first electrode layers stacked in a first direction, a first semiconductor layer piercing the first electrode layers in a first direction, a first insulating film surrounding the first semiconductor layer, and a semiconductor base connected to the first semiconductor layer. The first insulating film includes a first film, a second film, and a third film provided in order in a second direction from the first semiconductor layer toward one of first electrode layers. Spacing in the first direction between the second film and the semiconductor base is wider than a film thickness of the third film in the second direction. A minimum width of an outer perimeter of the first semiconductor layer is substantially the same as a width of an outer perimeter at a portion of the first semiconductor layer piercing the most proximal first electrode layer.Type: ApplicationFiled: November 26, 2019Publication date: March 26, 2020Applicant: TOSHIBA MEMORY CORPORATIONInventors: Reiko KOMIYA, Tatsuo IZUMI, Takaya YAMANAKA, Takeshi NAGATOMO, Karin TAKAGI
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Patent number: 10529735Abstract: A memory device includes first electrode layers stacked in a first direction, a first semiconductor layer piercing the first electrode layers in a first direction, a first insulating film surrounding the first semiconductor layer, and a semiconductor base connected to the first semiconductor layer. The first insulating film includes a first film, a second film, and a third film provided in order in a second direction from the first semiconductor layer toward one of first electrode layers. Spacing in the first direction between the second film and the semiconductor base is wider than a film thickness of the third film in the second direction. A minimum width of an outer perimeter of the first semiconductor layer is substantially the same as a width of an outer perimeter at a portion of the first semiconductor layer piercing the most proximal first electrode layer.Type: GrantFiled: September 11, 2018Date of Patent: January 7, 2020Assignee: TOSHIBA MEMORY CORPORATIONInventors: Reiko Komiya, Tatsuo Izumi, Takaya Yamanaka, Takeshi Nagatomo, Karin Takagi
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Patent number: 10431311Abstract: According to one embodiment, a semiconductor memory includes includes conductors, a pillar through the conductors, a controller. The pillar includes a first pillar portion, a second pillar portion, and a joint portion between the first pillar portion and the second pillar portion. Each of the portions where the pillar and the conductors cross functions as a transistor. Among the conductors through the first pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a first dummy word line and a first word line. Among the conductors through the second pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a second dummy word line and a second word line.Type: GrantFiled: August 7, 2018Date of Patent: October 1, 2019Assignee: Toshiba Memory CorporationInventors: Tatsuo Izumi, Reiko Komiya
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Publication number: 20190287997Abstract: A memory device includes first electrode layers stacked in a first direction, a first semiconductor layer piercing the first electrode layers in a first direction, a first insulating film surrounding the first semiconductor layer, and a semiconductor base connected to the first semiconductor layer. The first insulating film includes a first film, a second film, and a third film provided in order in a second direction from the first semiconductor layer toward one of first electrode layers. Spacing in the first direction between the second film and the semiconductor base is wider than a film thickness of the third film in the second direction. A minimum width of an outer perimeter of the first semiconductor layer is substantially the same as a width of an outer perimeter at a portion of the first semiconductor layer piercing the most proximal first electrode layer.Type: ApplicationFiled: September 11, 2018Publication date: September 19, 2019Applicant: Toshiba Memory CorporationInventors: Reiko Komiya, Tatsuo Izumi, Takaya Yamanaka, Takeshi Nagatomo, Karin Takagi
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Publication number: 20190189218Abstract: According to one embodiment, a semiconductor memory includes includes conductors, a pillar through the conductors, a controller. The pillar includes a first pillar portion, a second pillar portion, and a joint portion between the first pillar portion and the second pillar portion. Each of the portions where the pillar and the conductors cross functions as a transistor. Among the conductors through the first pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a first dummy word line and a first word line. Among the conductors through the second pillar portion, the conductor most proximal to the joint portion and one of the other conductors respectively function as a second dummy word line and a second word line.Type: ApplicationFiled: August 7, 2018Publication date: June 20, 2019Applicant: Toshiba Memory CorporationInventors: Tatsuo IZUMI, Reiko KOMIYA