MEMORY DEVICE
A memory device includes a conductive layer, a plurality of first electrode layers, a first semiconductor layer extending through the plurality of first electrode layers in a first direction toward the plurality of first electrode layers from the conductive layer, a first insulating film including a tunneling insulator film, a charge-trapping film and a blocking insulator film, a second electrode layer, and a semiconductor base. The charge-trapping film is spaced along the first direction from the semiconductor base, a distance in the first direction between the charge-trapping film and the semiconductor base is larger than a thickness of the blocking insulator film in a second direction toward the plurality of first electrode layers from the first semiconductor layer.
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This application is a continuation of U.S. application Ser. No. 16/695,749, filed Nov. 26, 2019, which is a continuation of U.S. application Ser. No. 16/127,634, filed Sep. 11, 2018 (now U.S. Pat. No. 10,529,735), which is based upon and claims the benefit of priority from Japanese Patent Application No. 2018-045703, filed on Mar. 13, 2018; the entire contents of each of which are incorporated herein by reference.
FIELDEmbodiments relate to a memory device.
BACKGROUNDA memory device that includes three-dimensionally arranged memory cells is being developed. For example, a NAND nonvolatile memory device includes multiple electrode layers and a semiconductor layer having a columnar configuration piercing the multiple electrode layers; and memory cells are provided between the semiconductor layer and the electrode layers. In a memory device having such a structure, the memory capacity can be increased by increasing the number of electrode layers. However, when the electrode layers are increased, the cell current that flows through the semiconductor layer piercing the electrode layers may decrease.
According to one embodiment, a memory device includes a conductive layer, a plurality of first electrode layers, a first semiconductor layer, a first insulating film, a second electrode layer and a semiconductor base. The plurality of first electrode layers are stacked above the conductive layer. The first semiconductor layer pierces the plurality of first electrode layers in a first direction, wherein the first direction is from the conductive layer toward the plurality of first electrode layers. The first insulating film is provided to surround the first semiconductor layer between the first semiconductor layer and the plurality of first electrode layers. The first insulating film includes a first film, a second film, and a third film provided in order in a second direction, wherein the second direction is from the first semiconductor layer toward one of the plurality of first electrode layers. The second electrode layer is provided between the conductive layer and the first electrode layer of the plurality of first electrode layers most proximal to the conductive layer. The semiconductor base is connected to the first semiconductor layer, and is provided to pierce the second electrode layer in the first direction between the conductive layer and the first semiconductor layer. A spacing in the first direction between the second film and a surface of the semiconductor base contacting the first semiconductor layer is wider than a film thickness of the third film in the second direction. A minimum width in the second direction of an outer perimeter of a portion of the first semiconductor layer surrounded with the first insulating film is substantially the same as a first width in the second direction of an outer perimeter of a portion of the first semiconductor layer piercing the most proximal first electrode layer. A second width in the second direction of an outer perimeter of the first semiconductor layer positioned at a level between the semiconductor base and the first insulating film is substantially the same as or wider than the first width, and is narrower than a third width in the second direction, wherein the third width is of an outer perimeter of the first insulating film covering the portion of the first semiconductor layer piercing the most proximal first electrode layer.
Embodiments will now be described with reference to the drawings. The same portions inside the drawings are marked with the same numerals; a detailed description is omitted as appropriate; and the different portions are described. The drawings are schematic or conceptual; and the relationships between the thicknesses and widths of portions, the proportions of sizes between portions, etc., are not necessarily the same as the actual values thereof. The dimensions and/or the proportions may be illustrated differently between the drawings, even in the case where the same portion is illustrated.
There are cases where the dispositions of the components are described using the directions of XYZ axes shown in the drawings. The X-axis, the Y-axis, and the Z-axis are orthogonal to each other. Hereinbelow, the directions of the X-axis, the Y-axis, and the Z-axis are described as an X-direction, a Y-direction, and a Z-direction. Also, there are cases where the Z-direction is described as upward and the direction opposite to the Z-direction is described as downward.
First EmbodimentAs shown in
The memory device 1 includes a memory cell region MCR and a draw-out region HUR. Multiple columnar bodies PB are provided in the memory cell region MCR. The columnar bodies PB each include columnar portions PB1 and PB2 and a connection portion JP. A semiconductor base SB is further provided between the source layer SL and the columnar body PB.
The columnar portion PB1 extends in a Z-direction and pierces the word lines WL1. The columnar portion PB2 extends in the Z-direction and pierces the word lines WL2 and the select gate SGD. The connection portion JP connects the columnar portion PB1 and the columnar portion PB2. The columnar portion PB1 is connected to the semiconductor base SB.
The semiconductor base SB extends in the Z-direction and pierces the select gate SGS. The columnar body PB is connected to the source layer SL via the semiconductor base SB. The columnar body PB also is connected to a bit line BL via a connection plug VB.
The draw-out region HUR includes end portions of the select gate SGS, the word lines WL1 and WL2, and the select gate SGD. As shown in
The draw-out region HUR further includes a columnar support body SP. The columnar support body SP is provided at the vicinity of the contact plugs CC, extends in the Z-direction, and pierces at least one of the word line WL1 or WL2 or the select gate SGD. The columnar support body SP includes a lower portion piercing the word lines WL1, an upper portion piercing the word lines WL2 and the select gate SGD, and the connection portion JP linking between the lower portion and the upper portion.
As shown in
The inter-layer insulating films 25 are provided between the word lines WL2 adjacent to each other in the Z-direction. The inter-layer insulating film 25 is further provided between the word line WL2 and the inter-layer insulating film 30. The inter-layer insulating film 30 covers the upper end of the columnar body PB.
The columnar body PB includes a memory film MF, a semiconductor layer SF, and an insulating core CA. The insulating core CA extends in the Z-direction in the interior of the columnar body PB. The semiconductor layer SF surrounds the insulating core CA and extends in the Z-direction. The memory film MF is positioned between the semiconductor layer SF and the word lines WL and extends in the Z-direction along the semiconductor layer SF. The memory film MF is positioned between the semiconductor layer SF and the select gate SGD. Hereinbelow, the word line WL1 and the word line WL2 are generally called the word line WL in the description.
The semiconductor layer SF is connected to the semiconductor base SB at the lower end of the semiconductor layer SF. The semiconductor base SB is connected to the source layer SL at the lower end of the semiconductor base SB and electrically connects the semiconductor layer SF and the source layer SL. An insulating film 31 is provided between the semiconductor base SB and the select gate SGS. An insulating film 33 is provided between the semiconductor base SB and the memory film MF.
The semiconductor layer SF is connected to the connection plug VB at the upper end of the semiconductor layer SF. The connection plug VB is provided inside the inter-layer insulating film 30 and electrically connects the semiconductor layer SF to the bit line BL provided on the inter-layer insulating film 30.
The memory device 1 includes a select transistor STS, memory cells MC, and a select transistor STD. The select transistor STD is provided at a portion where the semiconductor layer SF crosses the select gate SGD. The memory cells MC are provided at portions where the semiconductor layer SF crosses the word lines WL. The select transistor STD includes a portion of the memory film MF as a gate insulating film. The memory cells MC include portions of the memory film MF as charge retaining portions.
The select transistor STS is provided at a portion where the semiconductor base SB pierces the select gate SGS. The insulating film 31 that is provided between the semiconductor base SB and the select gate SGS functions as a gate insulating film of the select transistor STS.
As shown in
The columnar support body SP is formed to pierce the end portions of the word lines WL and the select gate SGD formed in the staircase configuration in the draw-out region HUR. Therefore, the number of the word lines WL and the select gates SGD crossing the columnar support body SP is different according to the position where the columnar support body SP is provided. In other words, the columnar support body SP is provided to pierce at least one word line WL counting from the word line WL of the lowermost layer.
The upper portion of the columnar support body SP is provided to pierce an insulating film 29 burying the end portions of the word lines WL formed in the staircase configuration. The upper end of the columnar support body SP is covered with the inter-layer insulating film 30 provided on the insulating film 29 and is electrically insulated from the interconnects of the upper layers (not illustrated).
As shown in
The tunneling insulating film TN is, for example, a silicon oxide film; and the charge trap film CT is, for example, a silicon nitride film. The blocking insulating film BLK is, for example, a silicon oxide film. The blocking insulating film BLK also may include an insulative metal oxide, e.g., aluminum oxide, etc.
The embodiment is not limited to the example; and, for example, memory cells MC having floating gate structures may be used. For example, instead of the charge trap film CT, the memory film MF may include conductive films at the portions positioned between the semiconductor layer SF and the word lines WL. The conductive films are positioned between the tunneling insulating film TN and the blocking insulating film BLK and are arranged to be separated from each other in the Z-direction.
The semiconductor layer SF has a width WS1 in an X-direction of the outer perimeter at a position crossing a word line WLB1 of the lowermost layer, a width WS2 in the X-direction of the outer perimeter at the lower end position of the memory film MF, and a width WS3 in the X-direction of the outer perimeter surrounded with the insulating film 33. In the case where the horizontal cross section of the semiconductor layer SF is substantially a circle, WS1, WS2, and WS3 are the outer diameters of the semiconductor layer SF at the respective positions.
Here, WS2 is the minimum width in the X-direction of the semiconductor layer SF and is substantially the same as WS1 in the embodiment. WS3 is substantially the same as WS2 or wider than WS2.
Because the insulating film 33 is provided on the semiconductor base SB, a spacing T1 between the lower end of the charge trap film CT and the surface where the semiconductor layer SF and the semiconductor base SB contact, i.e., the upper surface of the semiconductor base SB, is wider than a film thickness TBLK of the blocking insulating film BLK. The memory film MF has a width WPB in the X-direction of the outer perimeter at a position contacting the word line WLB1; and WS3 is narrower than WPB.
A method for manufacturing the memory device 1 according to the first embodiment will now be described with reference to
As shown in
The memory hole MH1 has a depth reaching the source layer SL from the upper surface of the inter-layer insulating film 21. For example, the memory hole MH1 is formed by selectively removing the inter-layer insulating films 13, 15, and 21 and the sacrificial films 17 using anisotropic RIE (Reactive Ion Etching).
The source layer SL is, for example, a portion of a silicon substrate, or a polysilicon layer provided on a silicon substrate (not illustrated) with an inter-layer insulating film (not illustrated) interposed. The inter-layer insulating films 13, 15, and 21 are, for example, silicon oxide films. The sacrificial films 17 are, for example, silicon nitride films.
As shown in
The semiconductor base SB is formed so that an upper surface SBT of the semiconductor base SB is positioned at a level between a sacrificial film 17A and a sacrificial film 17B. Here, the sacrificial film 17B is the sacrificial film 17 of the lowermost layer of the multiple sacrificial films 17. The sacrificial film 17A is the sacrificial film 17 adjacent to the sacrificial film 17B in the Z-direction.
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In the following drawings, the inter-layer insulating films 21 and 25 are described as being formed as one body as the inter-layer insulating film 23.
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At this time, the insulating film 33 protects the semiconductor base SB from the etchant of the sacrificial layers 35 and 37. Thereby, the etching of the semiconductor base SB and the lowering of the position of the upper surface SBT of the semiconductor base SB (referring to
In the embodiment, the memory hole MH that reaches the insulating film 33 from the inter-layer insulating film 25T can be formed easily by connecting the memory hole MH1 and the memory hole MH2. For example, in the case where the aspect ratio (the depth divided by the diameter of the bottom surface) of the memory hole MH is large, it is difficult to form a memory hole MH having a uniform diameter in the depth direction. In the embodiment, a memory hole MH having the desired high aspect ratio can be realized by connecting the memory hole MH1 and the memory hole MH2 which have small aspect ratios. Further, the positional alignment of the memory hole MH2 with respect to the memory hole MH1 is easy by providing the connection portion JP which has an enlarged diameter between the memory hole MH1 and the memory hole MH2.
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For example, the semiconductor layer SF2 contacts the surface of the semiconductor base SB that is not damaged by the anisotropic RIE at the enlarged bottom portion of the memory hole MH. Thereby, the contact resistance between the semiconductor layer SF (referring to
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The columnar body PB supports the inter-layer insulating films 15, 23, and 25 in the memory cell region MCR and maintains the space between the inter-layer insulating films. Also, the columnar support body SP (referring to
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The source contact LI is electrically insulated from the word lines WL and the select gates SGS and SGD by an insulating film 45. The insulating film 45 is, for example, a silicon oxide film and is provided on the inner wall of the slit ST.
Continuing, the contact plugs CC and the interconnects of the upper layers that are connected respectively to the word lines WL and the select gates SGS and SGD (referring to
In the memory device 2 as shown in
In the memory device 2, for example, there are cases where the current (hereinbelow, the cell current) that flows through the semiconductor layer SF when reading data from the memory cells MC is blocked by the insulating film 33 and the lower end MFB of the memory film MF. Conversely, in the memory device 1 shown in
In the memory device 3 as shown in
The width WS3 in the X-direction of the outer perimeter of the semiconductor layer SF contacting the inter-layer insulating film 15 is substantially the same as or wider than a width WMH in the X-direction of the outer perimeter of the memory film MF at the level of the word line WLB1. A spacing T2 between the upper surface of the semiconductor base SB and the lower end of the charge trap film CT is wider than a film thickness TMF of the memory film MF. For example, in the case where the horizontal cross section of the memory hole MH is substantially a circle, WMH is the diameter of the memory hole MH.
In the memory device 3, the width WS3 of the outer perimeter of the semiconductor layer SF at the lower end of the memory film MF can be set to be substantially the same as the width WS1 of the outer perimeter of the semiconductor layer SF at the level of the word line WLB1; and the channel resistance between the semiconductor layer SF and the semiconductor base SB can be reduced and the cell current can be large by enlarging, in the horizontal direction, the portion of the semiconductor layer SF positioned between the memory film MF and the semiconductor base SB.
In the memory device 4 as shown in
For example, the memory device 4 can be formed by omitting the formation of the semiconductor base SB and the formation of the insulating film 33 shown in
In the memory device 4 as well, the channel resistance at the lower end of the semiconductor layer SF can be reduced. Also, the contact resistance between the semiconductor layer SF and the source layer SL can be reduced because a portion of the semiconductor layer SF contacts a portion of the source layer SL not damaged by the RIE. Thereby, a cell current ICEL that flows in the source contact LI from the semiconductor layer SF via the source layer SL can be increased.
In the embodiment as recited above, the bottom portion of the memory hole MH is enlarged by partially removing the insulating film 33 and the lower end MFB of the memory film MF. Thereby, the resistance of the semiconductor layer SF provided in the interior of the memory hole MH can be reduced. For example, even in the case where the number of stacks of the word lines WL increases and the entire channel length of the memory cells MC increases, it is possible to prevent the decrease of the cell current by reducing the channel resistance at the lower portion of the semiconductor layer SF.
Second EmbodimentAs shown in
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In this process, the end surfaces of the sacrificial films 17 exposed at the inner wall of the support hole HR also are oxidized; and insulating films 55 are formed. The sacrificial films 17 are, for example, silicon nitride films; and the insulating films 55 are, for example, silicon oxide films. For example, the insulating film 53 may be deposited on the inner surface of the support hole HR using CVD.
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For example, the memory hole MH1 is formed by selectively removing the inter-layer insulating films 13, 15, and 21 and the sacrificial films 17 by using a resist mask 57. As shown in
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Further, the insulating film 33 is formed by oxidizing the semiconductor base SB in the memory hole MH1. In the support hole HR, the oxidization of the source layer SL and the sacrificial films 17 progresses; and the film thicknesses of the insulating films 53 and 55 become thick. Although the sacrificial films 17 that are exposed at the inner wall of the memory hole MH1 also are oxidized in the oxidization, insulating films that are formed on the end surfaces of the sacrificial films 17 inside the memory hole MH1 are not illustrated in
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Then, the word lines WL and the select gates SGS and SGD are formed by the manufacturing processes shown in FIGS. 12A to 14B. In the embodiment, the semiconductor layer SF that is provided in the interior of the columnar support body SP is electrically insulated from the source layer SL by the insulating film 53. For example, even in the case where the contact plug CC contacts the semiconductor layer SF due to positional shift of the mask alignment, etc., the electrical insulation between the source layer SL and the contact plug CC can be maintained.
Third EmbodimentIn the columnar portion PB1 as shown in
A method for manufacturing the memory device 6 according to the third embodiment will now be described with reference to
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In the embodiment, the blocking insulating films BLK1 and the blocking insulating film BLK2 are formed separately in the columnar portion PB1 and the columnar portion PB2. Thereby, the electrical characteristics of the memory film MF can be controlled independently between the columnar portions PB1 and PB2. For example, a coupling ratio difference that is caused by an outer diameter difference between the columnar portions PB1 and PB2 can be reduced.
Embodiments will now be described with reference to the drawings. The same portions inside the drawings are marked with the same numerals; a detailed description is omitted as appropriate; and the different portions are described. The drawings are schematic or conceptual; and the relationships between the thicknesses and widths of portions, the proportions of sizes between portions, etc., are not necessarily the same as the actual values thereof. The dimensions and/or the proportions may be illustrated differently between the drawings, even in the case where the same portion is illustrated.
Claims
1. A manufacturing method of a nonvolatile semiconductor memory device comprising:
- forming a conductive layer;
- forming first layers and second layers alternately in a first direction above the conductive layer, the first direction being perpendicular to a surface of the conductive layer;
- forming a first hole in the first layers and the second layers, the first hole extending in the first direction;
- forming an insulating film in the first hole;
- forming an sacrificial material in the first hole, the insulating film being between the conductive layer and the sacrificial material;
- forming third layers and fourth layers alternately in the first direction above the first and second layers;
- forming a second hole in the third layers and the fourth layers, the second hole extending in the first direction to reach the sacrificial material;
- removing the sacrificial material through the second hole; and
- forming a memory layer in the first hole and the second hole.
2. The manufacturing method according to claim 1, further comprising:
- forming a semiconductor layer on the memory layer in the first hole and the second hole.
3. The manufacturing method according to claim 1, further comprising:
- forming a semiconductor base on the conductive layer in the first hole.
4. The manufacturing method according to claim 3, wherein the insulating film is formed on the semiconductor base.
5. The manufacturing method according to claim 3, wherein the insulating film is formed by oxidizing a portion of the semiconductor base.
6. The manufacturing method according to claim 3, wherein the semiconductor base includes the same material as a material of the sacrificial material.
7. The manufacturing method according to claim 3, wherein the semiconductor base and the sacrificial material each include silicon.
8. The manufacturing method according to claim 1, further comprising:
- forming a slit in the first layers, the second layers, the third layers and the fourth layers,
- removing the first layers and the third layers through the slit to form spaces; and
- forming conductive materials in the spaces.
9. The manufacturing method according to claim 3, further comprising:
- forming a slit in the first layers, the second layers, the third layers and the fourth layers;
- removing the first layers and the third layers through the slit to form spaces; and
- forming conductive materials in the spaces.
10. The manufacturing method according to claim 9, further comprising:
- forming a gate insulating film on a side surface of the semiconductor base exposed after removing the first layers and the third layers and before forming the conductive materials.
11. The manufacturing method according to claim 9, wherein the gate insulating film is formed by oxidizing a portion of the semiconductor base.
12. The manufacturing method according to claim 1, further comprising:
- forming an inter-layer insulating layer above the first layers and the second layers; and
- forming a connection hole in the inter-layer insulating layer before forming the sacrificial material, the connection hole having a larger diameter than a diameter of the first hole.
13. The manufacturing method according to claim 1, wherein the memory layer includes a blocking insulating layer, a charge trap layer and a tunneling insulating layer.
14. A manufacturing method of a nonvolatile semiconductor memory device comprising:
- forming a conductive layer;
- forming first layers and second layers alternately in a first direction above the conductive layer, the first direction being perpendicular to a surface of the conductive layer;
- forming a first hole in the first layers and the second layers, the first hole extending in the first direction;
- forming a semiconductor base on the conductive layer in the first hole
- forming an insulating film on the semiconductor base in the first hole;
- forming an sacrificial material in the first hole, the insulating film being between the conductive layer and the sacrificial material;
- forming third layers and fourth layers alternately in the first direction above the first and second layers;
- forming a second hole in the third layers and the fourth layers, the second hole extending in the first direction to reach the sacrificial material;
- removing the sacrificial material through the second hole;
- forming a memory layer in the first hole and the second hole; and
- forming a semiconductor layer on the memory layer in the first hole and the second hole.
15. The manufacturing method according to claim 14, wherein the insulating film is formed by oxidizing a portion of the semiconductor base.
16. The manufacturing method according to claim 14, wherein the semiconductor base and the sacrificial material each include silicon.
17. The manufacturing method according to claim 14, further comprising:
- forming a slit in the first layers, the second layers, the third layers and the fourth layers;
- removing the first layers and the third layers through the slit to form spaces; and
- forming conductive materials in the spaces.
18. The manufacturing method according to claim 14, further comprising:
- forming a gate insulating film on a side surface of the semiconductor base exposed after removing the first layers and the third layers and before forming the conductive materials by oxidizing a portion of the semiconductor base.
19. The manufacturing method according to claim 14, further comprising:
- forming an inter-layer insulating layer above the first layers and the second layers; and
- forming a connection hole in the inter-layer insulating layer before forming the sacrificial material, the connection hole having a larger diameter than a diameter of the first hole.
20. The manufacturing method according to claim 14, wherein the memory layer includes a blocking insulating layer, a charge trap layer and a tunneling insulating layer.
Type: Application
Filed: Apr 28, 2021
Publication Date: Aug 12, 2021
Applicant: TOSHIBA MEMORY CORPORATION (Minato-ku)
Inventors: Reiko KOMIYA (Nagoya), Tatsuo IZUMI (Yokkaichi), Takaya YAMANAKA (Yokkaichi), Takeshi NAGATOMO (Yokkaichi), Karin TAKAGI (Yokkaichi)
Application Number: 17/242,870