Patents by Inventor Reinaldo Vega

Reinaldo Vega has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • RRAM CROSSBAR ARRAY STRUCTURE FOR MULTI-TASK LEARNING
    Publication number: 20200143233
    Abstract: Provided are embodiments of a multi-task learning system with hardware acceleration that includes a resistive random access memory crossbar array. Aspects of the invention includes an input layer that has one or more input layer nodes for performing one or more tasks of the multi-task learning system, a hidden layer that has one or more hidden layer nodes, and a shared hidden layer that has one or more shared hidden layer nodes which represent a parameter, wherein the shared hidden layer nodes are coupled to each of the one or more hidden layer nodes of the hidden layer.
    Type: Application
    Filed: November 2, 2018
    Publication date: May 7, 2020
    Inventors: Takashi Ando, Reinaldo Vega, Hari Mallela
  • Vertical fin field effect transistor with air gap spacers
    Patent number: 10644104
    Abstract: A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: May 5, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hari V. Mallela, Robert R. Robison, Reinaldo A. Vega, Rajasekhar Venigalla
  • External resistance reduction with embedded bottom source/drain for vertical transport FET
    Patent number: 10636874
    Abstract: A method is presented for reducing external resistance of a vertical field-effect-transistor (FET). The method includes forming a plurality of fins over a sacrificial layer disposed over a substrate, selectively removing the sacrificial layer to form an etch stop layer in direct contact with the substrate, disposing embedded bottom source/drain regions between a bottom portion of the plurality of fins and the etch stop layer, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, forming top spacers adjacent the top portions of the plurality of fins, and forming top source/drain regions over the top portions of the plurality of fins.
    Type: Grant
    Filed: August 29, 2018
    Date of Patent: April 28, 2020
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Reinaldo Vega, Jingyun Zhang, Miaomiao Wang
  • STRUCTURE AND METHODOLOGY FOR DETERMINING TEST PAD INTEGRITY
    Publication number: 20200124638
    Abstract: A test probe assembly for determining the integrity of a test pad of a semiconductor wafer. The test probe assembly includes a probe card, a plurality of test probes mounted to the probe card, a fiber optic lead mounted to each test probe and arranged to direct incident light toward individual test pads of the semiconductor wafer and a plurality of photodetectors arranged about the probe card. Individual photodetectors are configured to receive light reflected off a dielectric coating of the test pad corresponding to a first set of light rays emitted by the test pad and configured to receive light reflected off a metallic base of the test pad corresponding to a second set of light rays emitted by the test pad, and to generate first and second output signals associated with the first and second sets of light rays to create image data of the individual test pads.
    Type: Application
    Filed: October 18, 2018
    Publication date: April 23, 2020
    Inventors: Kushagra Sinha, Pablo Nieves, Reinaldo Vega
  • STRUCTURE AND METHODOLOGY FOR HIGH INTENSITY TEST PROBE ALIGNMENT TO DEVICE TEST PADS
    Publication number: 20200124663
    Abstract: A test probe assembly includes a probe card, a plurality of test probes mounted to the probe card with each of the test probes having a probe tip segment and a probe end for positioning adjacent respective individual test pads of a semiconductor wafer, and a fiber optic lead mounted to each test probe. The fiber optic leads are arranged to direct incident light toward respective individual test pads of the semiconductor wafer. A plurality of photodetectors may be arranged about the probe card with individual photodetectors configured for reception of light reflected off the respective individual test pads to emit output signals used to generate image data representative of the individual test pads on the semiconductor wafer. The image data may be utilized to align the test pads with the test probes for subsequent testing.
    Type: Application
    Filed: October 18, 2018
    Publication date: April 23, 2020
    Inventors: Pablo Nieves, Kushagra Sinha, Reinaldo Vega
  • NANOSHEET FIELD EFFECT TRANSISTORS WITH PARTIAL INSIDE SPACERS
    Publication number: 20200098893
    Abstract: A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.
    Type: Application
    Filed: November 14, 2019
    Publication date: March 26, 2020
    Inventors: Michael A. Guillorn, Terence B. Hook, Robert R. Robison, Reinaldo A. Vega, Rajasekhar Venigalla
  • FIN OXIDATION BY FLOWABLE OXIDE FILL AND STEAM ANNEAL TO MITIGATE LOCAL LAYOUT EFFECTS
    Publication number: 20200083089
    Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin, which includes a channel layer and an intermediate semiconductor layer, to electrically isolate active regions of the semiconductor fin by forming an oxide that fully penetrates the channel layer and the intermediate semiconductor layer. A semiconductor device is formed on each of the active regions.
    Type: Application
    Filed: September 10, 2018
    Publication date: March 12, 2020
    Inventors: Huimei Zhou, Gen Tsutsui, Veeraraghavan S. Basker, Andrew M. Greene, Dechao Guo, Huiming Bu, Reinaldo Vega
  • FIN ISOLATION TO MITIGATE LOCAL LAYOUT EFFECTS
    Publication number: 20200083088
    Abstract: Integrated chips and methods of forming the same include oxidizing a portion of a semiconductor fin to electrically isolate active regions of the semiconductor fin. A semiconductor device is formed on each of the active regions.
    Type: Application
    Filed: September 10, 2018
    Publication date: March 12, 2020
    Inventors: Huimei Zhou, Gen Tsutsui, Andrew M. Greene, Dechao Guo, Huiming Bu, Robert Robison, Veeraraghavan S. Basker, Reinaldo Vega
  • Gate-all-around field effect transistor having multiple threshold voltages
    Patent number: 10586854
    Abstract: One example of an apparatus includes a conducting channel region. The conducting channel region includes a plurality of epitaxially grown, in situ doped conducting channels arranged in a spaced apart relation relative to each other. A source positioned at a first end of the conducting channel region, and a drain positioned at a second end of the conducting channel region. A gate surrounds all sides of the conducting channel region and fills in spaces between the plurality of epitaxially grown, in situ doped conducting channels.
    Type: Grant
    Filed: May 10, 2018
    Date of Patent: March 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Ruqiang Bao, Michael A. Guillorn, Terence Hook, Robert R. Robison, Reinaldo Vega, Tenko Yamashita
  • EXTERNAL RESISTANCE REDUCTION WITH EMBEDDED BOTTOM SOURCE/DRAIN FOR VERTICAL TRANSPORT FET
    Publication number: 20200075723
    Abstract: A method is presented for reducing external resistance of a vertical field-effect-transistor (FET). The method includes forming a plurality of fins over a sacrificial layer disposed over a substrate, selectively removing the sacrificial layer to form an etch stop layer in direct contact with the substrate, disposing embedded bottom source/drain regions between a bottom portion of the plurality of fins and the etch stop layer, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, forming top spacers adjacent the top portions of the plurality of fins, and forming top source/drain regions over the top portions of the plurality of fins.
    Type: Application
    Filed: August 29, 2018
    Publication date: March 5, 2020
    Inventors: Choonghyun Lee, Reinaldo Vega, Jingyun Zhang, Miaomiao Wang
  • MULTI-THRESHOLD VERTICAL FETS WITH COMMON GATES
    Publication number: 20200051979
    Abstract: Multi-voltage threshold vertical transport transistors and methods of fabrication generally include forming the transistors with vertically oriented silicon fin channels for both the n-type doped field effect transistors (nFET) and the p-type doped field effect transistors (pFET). A silicon oxynitride interfacial layer is provided on sidewalls of the fins in the nFET and a silicon dioxide interfacial with aluminum is provided on sidewalls of the fins in the pFET to provide an aluminum induced dipole. A high k dielectric overlays the interfacial layers and a common work function metal overlays the high k dielectric layer to define a gate structure.
    Type: Application
    Filed: August 13, 2018
    Publication date: February 13, 2020
    Inventors: Takashi Ando, Reinaldo Vega, Choonghyun Lee, Hari Mallela, Li-Wen Hung
  • Nanosheet field effect transistors with partial inside spacers
    Patent number: 10559670
    Abstract: A method of forming a nanosheet device, including forming a channel stack on a substrate, where the channel stack includes at least one nanosheet channel layer and at least one sacrificial release layer, forming a stack cover layer on at least a portion of the channel stack, forming a dummy gate on at least a portion of the stack cover layer, wherein at least a portion of the at least one nanosheet channel layer and at least one sacrificial release layer is exposed on opposite sides of the dummy gate, removing at least a portion of the at least one sacrificial release layer on each side of the dummy gate to form a sacrificial supporting rib, and forming an inner spacer layer on exposed portions of the at least one nanosheet channel layer and at least one sacrificial supporting rib.
    Type: Grant
    Filed: October 30, 2017
    Date of Patent: February 11, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Michael A. Guillorn, Terence B. Hook, Robert R. Robison, Reinaldo A. Vega, Rajasekhar Venigalla
  • SELF ALIGNED REPLACEMENT METAL SOURCE/DRAIN FINFET
    Publication number: 20190326406
    Abstract: A fin-shaped field effect transistor (finFET) device comprising includes a substrate. an insulating layer displaced over the substrate, and a fin. The device also includes a gate formed over the fin, the gate including: a gate stack; and a high-k dielectric on opposing side of the gate stack. The device further includes metallic source and drain regions formed over the fin and on opposing sides of the gate.
    Type: Application
    Filed: July 2, 2019
    Publication date: October 24, 2019
    Inventors: Emre Alptekin, Robert R. Robison, Reinaldo A. Vega
  • NANOWIRE ENABLED SUBSTRATE BONDING AND ELECTRICAL CONTACT FORMATION
    Publication number: 20190319006
    Abstract: A technique relates to a semiconductor device. First nanowires are formed on a first substrate, the first nanowires being electrically coupled to one or more first electrical sites on the first substrate. Second nanowires are formed on a second substrate, the second nanowires being electrically coupled to one or more second electrical sites on the second substrate. The first nanowires and the second nanowires are electrically coupled such that the one or more first electrical sites are electrically coupled to the one or more second electrical sites.
    Type: Application
    Filed: April 11, 2018
    Publication date: October 17, 2019
    Inventors: Li-Wen HUNG, Reinaldo VEGA, Hari MALLELA
  • VERTICAL FET DEVICES WITH MULTIPLE CHANNEL LENGTHS
    Publication number: 20190295897
    Abstract: A semiconductor device comprises a first source/drain region arranged on a semiconductor substrate, a second source/drain region arranged on the semiconductor substrate, a bottom spacer arranged on the first source/drain region, and a bottom spacer arranged on the second source/drain region. A first gate stack having a first length is arranged on the first source/drain region. A second gate stack having a second length is arranged on the second source/drain region, the first length is shorter than the second length. A top spacer is arranged on the first gate stack, and a top spacer is arranged on the second gate stack.
    Type: Application
    Filed: June 12, 2019
    Publication date: September 26, 2019
    Inventors: Hari V. Mallela, Reinaldo A. Vega, Rajasekhar Venigalla
  • Vertical FET devices with multiple channel lengths
    Patent number: 10424515
    Abstract: A semiconductor device comprises a first source/drain region arranged on a semiconductor substrate, a second source/drain region arranged on the semiconductor substrate, a bottom spacer arranged on the first source/drain region, and a bottom spacer arranged on the second source/drain region. A first gate stack having a first length is arranged on the first source/drain region. A second gate stack having a second length is arranged on the second source/drain region, the first length is shorter than the second length. A top spacer is arranged on the first gate stack, and a top spacer is arranged on the second gate stack.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: September 24, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hari V. Mallela, Reinaldo A. Vega, Rajasekhar Venigalla
  • Self aligned replacement metal source/drain finFET
    Patent number: 10418450
    Abstract: A fin-shaped field effect transistor (finFET) device comprising includes a substrate, an insulating layer displaced over the substrate, and a fin. The device also includes a gate formed over the fin, the gate including: a gate stack; and a high-k dielectric on opposing side of the gate stack. The device further includes metallic source and drain regions formed over the fin and on opposing sides of the gate.
    Type: Grant
    Filed: April 22, 2016
    Date of Patent: September 17, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Emre Alptekin, Robert R. Robison, Reinaldo A Vega
  • MULTIPLE-THRESHOLD NANOSHEET TRANSISTORS
    Publication number: 20190252495
    Abstract: Semiconductor devices and methods of making the same include forming a stack of alternating layers of channel material and sacrificial material. The sacrificial material is etched away to free the layers of channel material. A gate stack is formed around the layers of channel material. At least one layer of channel material is deactivated. Source and drain regions are formed in contact with the at least one layer of active channel material.
    Type: Application
    Filed: April 26, 2019
    Publication date: August 15, 2019
    Inventors: Ruqiang Bao, Michael A. Guillorn, Terence B. Hook, Nicolas J. Loubet, Robert R. Robison, Reinaldo A. Vega, Tenko Yamashita
  • Patterned sidewall smoothing using a pre-smoothed inverted tone pattern
    Patent number: 10381463
    Abstract: Embodiments are directed to a method and resulting structures for smoothing the sidewall roughness of a post-etched film. A sacrificial layer is formed on a substrate. A patterned mask is formed by removing portions of the sacrificial layer to expose a surface of the substrate. The sidewalls of the patterned mask are smoothed and a target layer is formed over the patterned mask and the substrate. Portions of the target layer are removed to expose a surface of the patterned mask and the patterned mask is removed.
    Type: Grant
    Filed: January 19, 2018
    Date of Patent: August 13, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Kafai Lai, Hari V. Mallela, Hiroyuki Miyazoe, Reinaldo A. Vega, Rajasekhar Venigalla
  • Multiple-threshold nanosheet transistors
    Patent number: 10340340
    Abstract: Semiconductor devices and methods of making the same include forming a stack of alternating layers of channel material and sacrificial material. The sacrificial material is etched away to free the layers of channel material. A gate stack is formed around the layers of channel material. At least one layer of channel material is deactivated. Source and drain regions are formed in contact with the at least one layer of active channel material.
    Type: Grant
    Filed: October 20, 2016
    Date of Patent: July 2, 2019
    Assignee: International Business Machines Corporation
    Inventors: Ruqiang Bao, Michael A. Guillorn, Terence B. Hook, Nicolas J. Loubet, Robert R. Robison, Reinaldo A. Vega, Tenko Yamashita