Patents by Inventor Reinaldo Vega

Reinaldo Vega has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Resistive memory with core and shell oxides and interface dipoles
    Patent number: 11145811
    Abstract: Resistive memory with core and shell oxides and interface dipoles for controlled filament formation is provided. In one aspect, a ReRAM device includes at least one ReRAM cell having a substrate; a bottom electrode disposed on the substrate; spacers formed from a low group electron negativity material disposed on the bottom electrode; a core formed from a high group electron negativity material present between the spacers; and a top electrode over and in contact with the spacers and the core, wherein a combination of the low group electron negativity material for the spacers and the high group electron negativity material for the core generates an interface dipole pointing toward the core. Methods of forming and operating a ReRAM device are also provided.
    Type: Grant
    Filed: October 16, 2019
    Date of Patent: October 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Jianshi Tang, Praneet Adusumilli, Reinaldo Vega
  • Device test pad probe card structure with individual probe manipulation capability
    Patent number: 11137418
    Abstract: A test probe assembly for use in testing a semiconductor wafer includes a probe card, a plurality of test probes mounted to the probe card and one or more piezoelectric elements mounted to each test probe. The piezoelectric elements are configured to move respective probe ends of the individual test probes in at least one direction to facilitate realignment of the probe ends for semiconductor wafer testing.
    Type: Grant
    Filed: March 4, 2019
    Date of Patent: October 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kushagra Sinha, Pablo Nieves, Reinaldo Vega
  • Test probe assembly with fiber optic leads and photodetectors
    Patent number: 11125780
    Abstract: A test probe assembly for determining the integrity of a test pad of a semiconductor wafer. The test probe assembly includes a probe card, a plurality of test probes mounted to the probe card, a fiber optic lead mounted to each test probe and arranged to direct incident light toward individual test pads of the semiconductor wafer and a plurality of photodetectors arranged about the probe card. Individual photodetectors are configured to receive light reflected off a dielectric coating of the test pad corresponding to a first set of light rays emitted by the test pad and configured to receive light reflected off a metallic base of the test pad corresponding to a second set of light rays emitted by the test pad, and to generate first and second output signals associated with the first and second sets of light rays to create image data of the individual test pads.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: September 21, 2021
    Assignee: International Business Machines Corporation
    Inventors: Kushagra Sinha, Pablo Nieves, Reinaldo Vega
  • Test probe assembly with fiber optic leads and photodetectors for testing semiconductor wafers
    Patent number: 11119148
    Abstract: A test probe assembly includes a probe card, a plurality of test probes mounted to the probe card with each of the test probes having a probe tip segment and a probe end for positioning adjacent respective individual test pads of a semiconductor wafer, and a fiber optic lead mounted to each test probe. The fiber optic leads are arranged to direct incident light toward respective individual test pads of the semiconductor wafer. A plurality of photodetectors may be arranged about the probe card with individual photodetectors configured for reception of light reflected off the respective individual test pads to emit output signals used to generate image data representative of the individual test pads on the semiconductor wafer. The image data may be utilized to align the test pads with the test probes for subsequent testing.
    Type: Grant
    Filed: October 18, 2018
    Date of Patent: September 14, 2021
    Assignee: International Business Machines Corporation
    Inventors: Pablo Nieves, Kushagra Sinha, Reinaldo Vega
  • CBRAM WITH CONTROLLED BRIDGE LOCATION
    Publication number: 20210242402
    Abstract: Devices with settable resistance and methods of forming the same include forming vertical dielectric structures from heterogeneous dielectric materials on a first electrode. A second electrode is formed on the vertical dielectric structures.
    Type: Application
    Filed: April 19, 2021
    Publication date: August 5, 2021
    Inventors: Jianshi Tang, Takashi Ando, Reinaldo Vega, Praneet Adusumilli
  • CBRAM with controlled bridge location
    Patent number: 11050023
    Abstract: Devices with settable resistance and methods of forming the same include forming vertical dielectric structures from heterogeneous dielectric materials on a first electrode. A second electrode is formed on the vertical dielectric structures.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: June 29, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jianshi Tang, Takashi Ando, Reinaldo Vega, Praneet Adusumilli
  • VERTICAL RESISTIVE MEMORY DEVICE WITH EMBEDDED SELECTORS
    Publication number: 20210167128
    Abstract: A vertical resistive switching memory device is provided that includes a resistive random access memory (ReRAM) stack embedded in a material stack of alternating layers of an interlayer dielectric material and a recessed electrode material. A selector device encapsulates a portion of the ReRAM stack and is present in an undercut region that is laterally adjacent to each of the recessed electrode material layers of the material stack.
    Type: Application
    Filed: December 3, 2019
    Publication date: June 3, 2021
    Inventors: Takashi Ando, Praneet Adusumilli, Reinaldo Vega, Cheng Chi
  • Vertical fin field effect transistor with air gap spacers
    Patent number: 11024709
    Abstract: A fin field effect transistor device with air gaps, including a source/drain layer on a substrate, one or more vertical fin(s) in contact with source/drain layer, a gate metal fill that forms a portion of a gate structure on each of the one or more vertical fin(s), and a bottom void space between the source/drain layer and the gate metal fill.
    Type: Grant
    Filed: March 5, 2020
    Date of Patent: June 1, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hari V. Mallela, Robert R. Robison, Reinaldo A. Vega, Rajasekhar Venigalla
  • Resistive Memory with Core and Shell Oxides and Interface Dipoles
    Publication number: 20210119122
    Abstract: Resistive memory with core and shell oxides and interface dipoles for controlled filament formation is provided. In one aspect, a ReRAM device includes at least one ReRAM cell having a substrate; a bottom electrode disposed on the substrate; spacers formed from a low group electron negativity material disposed on the bottom electrode; a core formed from a high group electron negativity material present between the spacers; and a top electrode over and in contact with the spacers and the core, wherein a combination of the low group electron negativity material for the spacers and the high group electron negativity material for the core generates an interface dipole pointing toward the core. Methods of forming and operating a ReRAM device are also provided.
    Type: Application
    Filed: October 16, 2019
    Publication date: April 22, 2021
    Inventors: Takashi Ando, Jianshi Tang, Praneet Adusumilli, Reinaldo Vega
  • Tapered Resistive Memory with Interface Dipoles
    Publication number: 20210098698
    Abstract: Tapered resistive memory devices with interface dipoles are provided. In one aspect, a ReRAM device includes: a bottom electrode; a core dielectric that is thermally conductive disposed on the bottom electrode; an oxide resistive memory cell disposed along outer sidewalls of the core dielectric, wherein the oxide resistive memory cell has inner edges adjacent to the core dielectric, and outer edges that are tapered; an outer coating disposed adjacent to the outer edges of the oxide resistive memory cell; and a top electrode disposed on the core dielectric, the oxide resistive memory cell, and the outer coating. A method of forming a ReRAM device as well as a method of operating a ReRAM device are also provided.
    Type: Application
    Filed: September 30, 2019
    Publication date: April 1, 2021
    Inventors: Reinaldo Vega, Takashi Ando, Jianshi Tang, Praneet Adusumilli
  • Vertical FET devices with multiple channel lengths
    Patent number: 10957603
    Abstract: A semiconductor device comprises a first source/drain region arranged on a semiconductor substrate, a second source/drain region arranged on the semiconductor substrate, a bottom spacer arranged on the first source/drain region, and a bottom spacer arranged on the second source/drain region. A first gate stack having a first length is arranged on the first source/drain region. A second gate stack having a second length is arranged on the second source/drain region, the first length is shorter than the second length. A top spacer is arranged on the first gate stack, and a top spacer is arranged on the second gate stack.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: March 23, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Hari V. Mallela, Reinaldo A. Vega, Rajasekhar Venigalla
  • Intercalation cells for multi-task learning
    Patent number: 10915811
    Abstract: An electro-chemical random-access memory (ECRAM) cell includes a substrate and a plurality of source-drain pairs positioned on a top surface of the substrate, each source-drain pair comprising a source and a drain. A channel at least partially overlays the substrate and the plurality of source-drain pairs, and a transfer layer at least partially overlays the channel. A gate at least partially overlays the transfer layer, the gate at least partially controlling a channel between each source-drain pair.
    Type: Grant
    Filed: September 18, 2019
    Date of Patent: February 9, 2021
    Assignee: International Business Machines Corporation
    Inventors: Takashi Ando, Jianshi Tang, Praneet Adusumilli, Reinaldo Vega
  • SELF ALIGNED REPLACEMENT METAL SOURCE/DRAIN FINFET
    Publication number: 20210028287
    Abstract: A fin-shaped field effect transistor (finFET) device comprising includes a substrate. an insulating layer displaced over the substrate, and a fin. The device also includes a gate formed over the fin, the gate including: a gate stack; and a high-k dielectric on opposing side of the gate stack. The device further includes metallic source and drain regions formed over the fin and on opposing sides of the gate.
    Type: Application
    Filed: October 14, 2020
    Publication date: January 28, 2021
    Applicant: Tessera, Inc.
    Inventors: Emre Alptekin, Robert R. Robison, Reinaldo A. Vega
  • External resistance reduction with embedded bottom source/drain for vertical transport FET
    Patent number: 10903318
    Abstract: A method is presented for reducing external resistance of a vertical field-effect-transistor (FET). The method includes forming a plurality of fins over a sacrificial layer disposed over a substrate, selectively removing the sacrificial layer to form an etch stop layer in direct contact with the substrate, disposing embedded bottom source/drain regions between a bottom portion of the plurality of fins and the etch stop layer, disposing encapsulation layers over the plurality of fins, recessing at least one of the encapsulation layers to expose top portions of the plurality of fins, forming top spacers adjacent the top portions of the plurality of fins, and forming top source/drain regions over the top portions of the plurality of fins.
    Type: Grant
    Filed: January 29, 2020
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Choonghyun Lee, Reinaldo Vega, Jingyun Zhang, Miaomiao Wang
  • Semiconductor device with mitigated local layout effects
    Patent number: 10892181
    Abstract: Integrated chips include a semiconductor fin that has a first active region and a second active region that are electrically separated by an oxide region that completely penetrates the semiconductor fin. A first semiconductor device is formed on the first active region. A second semiconductor device formed on the second active region.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: January 12, 2021
    Assignee: International Business Machines Corporation
    Inventors: Huimei Zhou, Gen Tsutsui, Veeraraghavan S. Basker, Andrew M. Greene, Dechao Guo, Huiming Bu, Reinaldo Vega
  • CBRAM WITH CONTROLLED BRIDGE LOCATION
    Publication number: 20210005813
    Abstract: Devices with settable resistance and methods of forming the same include forming vertical dielectric structures from heterogeneous dielectric materials on a first electrode. A second electrode is formed on the vertical dielectric structures.
    Type: Application
    Filed: July 1, 2019
    Publication date: January 7, 2021
    Inventors: Jianshi Tang, Takashi Ando, Reinaldo Vega, Praneet Adusumilli
  • Paired intercalation cells for drift migration
    Patent number: 10885979
    Abstract: A method is presented for mitigating conductance drift in intercalation cells for neuromorphic computing. The method includes forming a first electro-chemical random access memory (ECRAM) structure over a substrate and forming a second ECRAM over the substrate, the first and second ECRAMs sharing a common contact. The common contact can be either a source contact or a drain contact. Each of the first and second ECRAMs can include a tungsten oxide layer, an electrolyte layer, and a gate contact.
    Type: Grant
    Filed: April 9, 2019
    Date of Patent: January 5, 2021
    Assignee: International Business Machines Corporation
    Inventors: Jianshi Tang, Praneet Adusumilli, Reinaldo Vega, Takashi Ando
  • VERTICAL INTERCALATION DEVICE FOR NEUROMORPHIC COMPUTING
    Publication number: 20200373354
    Abstract: A semiconductor device with an array of vertically stacked electrochemical random-access memory (ECRAM) devices, includes holes formed in a vertical stack of horizontal electrodes. The horizontal electrodes are horizontally aligned and stacked vertically at different vertical levels within the vertical stack and separated by first fill layers. The semiconductor device includes a stack deposition, including a channel layer, and an electrolyte layer, formed over the vertical stack and holes. Selector layers fill holes. The selector layers include an inner selector layer and outer selector layers. The channel layer, the electrolyte layer and outer selector layers are recessed to the inner selector layer and a fill layer is deposited over the vertical stack. The fill layer has been reduced down to the top of the inner selector layer.
    Type: Application
    Filed: May 24, 2019
    Publication date: November 26, 2020
    Inventors: Jianshi Tang, Takashi Ando, Reinaldo Vega, Praneet Adusumilli
  • Nanowire enabled substrate bonding and electrical contact formation
    Patent number: 10833048
    Abstract: A technique relates to a semiconductor device. First nanowires are formed on a first substrate, the first nanowires being electrically coupled to one or more first electrical sites on the first substrate. Second nanowires are formed on a second substrate, the second nanowires being electrically coupled to one or more second electrical sites on the second substrate. The first nanowires and the second nanowires are electrically coupled such that the one or more first electrical sites are electrically coupled to the one or more second electrical sites.
    Type: Grant
    Filed: April 11, 2018
    Date of Patent: November 10, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Li-Wen Hung, Reinaldo Vega, Hari Mallela
  • RESISTIVE MEMORY WITH EMBEDDED METAL OXIDE FIN FOR GRADUAL SWITCHING
    Publication number: 20200343448
    Abstract: A method is presented for enabling heat dissipation in resistive random access memory (RRAM) devices. The method includes forming a first thermal conducting layer over a bottom electrode, depositing a metal oxide liner over the first thermal conducting layer, forming a second thermal conducting layer over the metal oxide liner, recessing the second thermal conducting layer to expose the first thermal conducting layer, and forming a top electrode in direct contact with the first and second thermal conducting layers.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 29, 2020
    Inventors: Takashi Ando, Praneet Adusumilli, Jianshi Tang, Reinaldo Vega