Patents by Inventor Rempei Nakata

Rempei Nakata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7094681
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a porous insulating film formed above the semiconductor substrate, the porous insulating film having a relative dielectric constant of 2.5 or less and including a first insulating material, at least a portion of pores in the porous insulating film having on the inner wall thereof a layer of a second insulating material which differs in nature from the first insulating material, and a plug and/or a wiring layer buried in the porous insulating film.
    Type: Grant
    Filed: November 6, 2003
    Date of Patent: August 22, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Keiji Fujita, Rempei Nakata, Hideshi Miyajima
  • Patent number: 7052971
    Abstract: A method for manufacturing a semiconductor device of the present invention includes, forming a first silicon oxide film by HDP-CVD so as to bury a recess portion in a three-dimensional portion formed in a surface region of a semiconductor workpiece to a position lower than an upper surface of the recess portion, and forming a second silicon oxide film by SOG on the first silicon oxide film so as to fill the recess portion.
    Type: Grant
    Filed: July 12, 2002
    Date of Patent: May 30, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yukio Nishiyama, Hirotaka Ogihara, Rempei Nakata
  • Publication number: 20050250311
    Abstract: The formation of an interlayer insulating film above a substrate, the formation of an insulating film of an organic material on the interlayer insulating film thereafter, and the irradiation of the insulating film of an organic material and the interlayer insulating film with electron beams, thereby curing at least the insulating film of an organic material, are proposed.
    Type: Application
    Filed: March 31, 2005
    Publication date: November 10, 2005
    Inventors: Hideshi Miyajima, Keiji Fujita, Hideaki Masuda, Rempei Nakata, Miyoko Shimada
  • Patent number: 6962870
    Abstract: A method of manufacturing a semiconductor device comprising forming a protective film on a surface of a lower-layer interconnection, and forming a multilayer-structured film by stacking a first porous film, a first non-porous film, a second porous film, and a second non-porous film on a surface of the protective film in this order, and forming a via hole and an interconnect trench. After a resist mask is removed, protective film exposed at a bottom of the via hole is removed. An upper-layer interconnection of dual damascene structure is formed by embedding an interconnect material in the via hole and the interconnect trench. The first non-porous film includes a first layer has a high etching selectivity ratio relative to the protective film, and a second layer has a high etching selectivity ratio relative to the resist mask and the second porous film.
    Type: Grant
    Filed: January 15, 2004
    Date of Patent: November 8, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideaki Masuda, Hideshi Miyajima, Rempei Nakata
  • Patent number: 6938638
    Abstract: A gas-circulating processing apparatus which comprises a processing chamber, a gas feeding piping, a gas supply piping, a first exhaust mechanism discharging a gas from the processing chamber, a second exhaust mechanism discharging a portion of a gas discharged from the first exhaust mechanism, a back pressure adjusting mechanism interposed between the first exhaust mechanism and the second exhaust mechanism to adjust a back pressure of the first exhaust mechanism, and a gas circulating piping which is configured to combine another portion of the gas that has been discharged from the first exhaust mechanism with a processing gas supplied from the gas supply piping, wherein the gas feeding piping has a larger inner diameter than that of the gas supply, or the processing gas is introduced into the first exhaust mechanism, or a first heater is provided to heat at least part of the circulating route.
    Type: Grant
    Filed: December 27, 2001
    Date of Patent: September 6, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Kubota, Rempei Nakata, Naruhiko Kaji, Itsuko Sakai, Takashi Yoda
  • Publication number: 20050026456
    Abstract: There is disclosed a film forming method comprising continuously discharging a solution adjusted so as to spread over a substrate by a given amount to the substrate through a discharge port disposed in a nozzle, moving the nozzle and substrate with respect to each other, and holding the supplied solution onto the substrate to form a liquid film, wherein a distance h between the discharge port of the nozzle and the substrate is set to be not less than 2 mm and to be in a range less than 5×10?5 q? (mm) given with respect to a surface tension ? (N/m) of the solution, discharge speed q (m/sec) of the solution continuously discharged through the discharge port, and a constant of 5×10?5 (m·sec/N)
    Type: Application
    Filed: August 27, 2004
    Publication date: February 3, 2005
    Inventors: Shinichi Ito, Tatsuhiko Ema, Kei Hayasaki, Rempei Nakata, Nobuhide Yamada, Katsuya Okumura
  • Publication number: 20050022732
    Abstract: There is disclosed a film forming method comprising continuously discharging a solution adjusted so as to spread over a substrate by a given amount to the substrate through a discharge port disposed in a nozzle, moving the nozzle and substrate with respect to each other, and holding the supplied solution onto the substrate to form a liquid film, wherein a distance h between the discharge port of the nozzle and the substrate is set to be not less than 2 mm and to be in a range less than 5×10?5 q? (mm) given with respect to a surface tension ? (N/m) of the solution, discharge speed q (m/sec) of the solution continuously discharged through the discharge port, and a constant of 5×10?5 (m·sec/N).
    Type: Application
    Filed: August 27, 2004
    Publication date: February 3, 2005
    Inventors: Shinichi Ito, Tatsuhiko Ema, Kei Hayasaki, Rempei Nakata, Nobuhide Yamada, Katsuya Okumura
  • Patent number: 6828684
    Abstract: There is provided a semiconductor device including a semiconductor substrate and a conductive layer above the semiconductor substrate, wherein the conductive layer contains copper, a surface region of the conductive layer contains at least one of C—H bonds and C—C bonds, and a total amount of C atoms forming the C—H bonds and C atoms forming the C—C bonds in the surface region is 30 atomic % or more of a whole amount of elements in the surface region.
    Type: Grant
    Filed: March 21, 2003
    Date of Patent: December 7, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ikegami, Rempei Nakata, Takashi Yoda, Nobuo Hayasaka, Yoshimi Hisatsune
  • Patent number: 6800569
    Abstract: There is disclosed a film forming method comprising continuously discharging a solution adjusted so as to spread over a substrate by a given amount to the substrate through a discharge port disposed in a nozzle, moving the nozzle and substrate with respect to each other, and holding the supplied solution onto the substrate to form a liquid film, wherein a distance h between the discharge port of the nozzle and the substrate is set to be not less than 2 mm and to be in a range less than 5×10−5 q&ggr; (mm) given with respect to a surface tension &ggr; (N/m) of the solution, discharge speed q (m/sec) of the solution continuously discharged through the discharge port, and a constant of 5×10−5 (m·sec/N).
    Type: Grant
    Filed: January 29, 2003
    Date of Patent: October 5, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shinichi Ito, Tatsuhiko Ema, Kei Hayasaki, Rempei Nakata, Nobuhide Yamada, Katsuya Okumura
  • Publication number: 20040175930
    Abstract: A method of manufacturing a semiconductor device comprising forming a protective film on a surface of a lower-layer interconnection, and forming a multilayer-structured film by stacking a first porous film, a first non-porous film, a second porous film, and a second non-porous film on a surface of the protective film in this order, and forming a via hole and an interconnect trench. After a resist mask is removed, protective film exposed at a bottom of the via hole is removed. An upper-layer interconnection of dual damascene structure is formed by embedding an interconnect material in the via hole and the interconnect trench.
    Type: Application
    Filed: January 15, 2004
    Publication date: September 9, 2004
    Inventors: Hideaki Masuda, Hideshi Miyajima, Rempei Nakata
  • Patent number: 6784092
    Abstract: Disclosed is a method for forming an insulating layer, including coating a substrate with an insulating film material to form a coated film, the insulating film material containing at least first and second polymers differing from each other in average molecular weight, and heating the coated film while irradiating the coated film with an electron beam.
    Type: Grant
    Filed: March 26, 2002
    Date of Patent: August 31, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideshi Miyajima, Miyoko Shimada, Rempei Nakata
  • Publication number: 20040135254
    Abstract: Disclosed is a semiconductor device comprising a semiconductor substrate, a porous insulating film formed above the semiconductor substrate, the porous insulating film having a relative dielectric constant of 2.5 or less and including a first insulating material, at least a portion of pores in the porous insulating film having on the inner wall thereof a layer of a second insulating material which differs in nature from the first insulating material, and a plug and/or a wiring layer buried in the porous insulating film.
    Type: Application
    Filed: November 6, 2003
    Publication date: July 15, 2004
    Inventors: Keiji Fujita, Rempei Nakata, Hideshi Miyajima
  • Patent number: 6746969
    Abstract: A method of manufacturing a semiconductor device comprises preparing a substrate to be treated, and forming an insulation film above the substrate, which includes applying an insulation film raw material above the substrate, the insulation film raw material including a substance or a precursor of the substance, the insulation film comprising the substance, curing the insulation film raw material by irradiating an electron beam on the substrate while heating the substrate in a reactor chamber, changing at least one of parameter selected from the group consisting of pressure in the reactor chamber, temperature of the substrate, type of gas having the substrate exposed thereto, flow rate of gas introduced into the reactor chamber, position of the substrate, and quantity of electrons incident to the substrate per unit time when the electron beam is being irradiated on the substrate.
    Type: Grant
    Filed: October 19, 2001
    Date of Patent: June 8, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Miyoko Shimada, Hideshi Miyajima, Rempei Nakata, Hideto Matsuyama, Katsuya Okumura, Masahiko Hasunuma, Nobuo Hayasaka
  • Patent number: 6703302
    Abstract: A method for manufacturing a semiconductor device, comprising forming a low dielectric constant insulating film containing Si atoms over a semiconductor substrate, heating the low dielectric constant insulating film while irradiating the low dielectric constant insulating film with an electron beam, and exposing the low dielectric constant insulating film during or after the heating to a gas promoting the bond formation of the Si atoms.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: March 9, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hideshi Miyajima, Miyoko Shimada, Rempei Nakata
  • Publication number: 20030211756
    Abstract: There is disclosed a film forming method comprising continuously discharging a solution adjusted so as to spread over a substrate by a given amount to the substrate through a discharge port disposed in a nozzle, moving the nozzle and substrate with respect to each other, and holding the supplied solution onto the substrate to form a liquid film, wherein a distance h between the discharge port of the nozzle and the substrate is set to be not less than 2 mm and to be in a range less than 5×10−5 q&ggr; (mm) given with respect to a surface tension &ggr; (N/m) of the solution, discharge speed q (m/sec) of the solution continuously discharged through the discharge port, and a constant of 5×10−5 (m·sec/N).
    Type: Application
    Filed: January 29, 2003
    Publication date: November 13, 2003
    Inventors: Shinichi Ito, Tatsuhiko Ema, Kei Hayasaki, Rempei Nakata, Nobuhide Yamada, Katsuya Okumura
  • Patent number: 6645881
    Abstract: A coating solution for used in a scan coating method contains a low vapor pressure solvent having a vapor pressure lower than 1 Torr (133.322 Pa) at room temperature.
    Type: Grant
    Filed: April 2, 2002
    Date of Patent: November 11, 2003
    Assignees: Kabushiki Kaisha Toshiba, JSR Corporation
    Inventors: Nobuhide Yamada, Rempei Nakata, Makoto Sugiura, Mutsuhiko Yoshioka, Takahiro Kitano, Shinji Kobayashi
  • Publication number: 20030181041
    Abstract: There is provided a semiconductor device including a semiconductor substrate and a conductive layer above the semiconductor substrate, wherein the conductive layer contains copper, a surface region of the conductive layer contains at least one of C—H bonds and C—C bonds, and a total amount of C atoms forming the C—H bonds and C atoms forming the C—C bonds in the surface region is 30 atomic % or more of a whole amount of elements in the surface region.
    Type: Application
    Filed: March 21, 2003
    Publication date: September 25, 2003
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ikegami, Rempei Nakata, Takashi Yoda, Nobuo Hayasaka, Yoshimi Hisatsune
  • Publication number: 20030143847
    Abstract: A method of forming a low dielectric constant insulating layer according to one aspect of the present invention includes: applying a material of low dielectric constant insulating layer containing a precursor of substances to constitute the low dielectric constant insulating layer or the substances above a substrate to be processed; and curing the material of low dielectric constant insulating layer by irradiating the material of low dielectric constant insulating layer with electron beams with the substrate to be processed being heated in a treatment chamber, the electron beams being incident on the material of low dielectric constant insulating layer from a direction different from a direction vertical to a surface of the material of low dielectric constant insulating layer above the substrate.
    Type: Application
    Filed: December 19, 2002
    Publication date: July 31, 2003
    Inventors: Hideshi Miyajima, Miyoko Shimada, Rempei Nakata
  • Publication number: 20030139063
    Abstract: A coating solution for used in a scan coating method contains a low vapor pressure solvent having a vapor pressure lower than 1 Torr (133.322 Pa) at room temperature.
    Type: Application
    Filed: April 2, 2002
    Publication date: July 24, 2003
    Inventors: Nobuhide Yamada, Rempei Nakata, Makoto Sugiura, Mutsuhiko Yoshioka, Takahiro Kitano, Shinji Kobayashi
  • Patent number: 6566261
    Abstract: There is provided a semiconductor device including a semiconductor substrate and a conductive layer above the semiconductor substrate, wherein the conductive layer contains copper, a surface region of the conductive layer contains at least one of C—H bonds and C—C bonds, and a total amount of C atoms forming the C—H bonds and C atoms forming the C—C bonds in the surface region is 30 atomic % or more of a whole amount of elements in the surface region.
    Type: Grant
    Filed: September 6, 2001
    Date of Patent: May 20, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Ikegami, Rempei Nakata, Takashi Yoda, Nobuo Hayasaka, Yoshimi Hisatsune