Patents by Inventor Ren?an Wang

Ren?an Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20040228415
    Abstract: An implementation of an MPEG-4 compliant post-filter for image data, which performs deblocking and deringing post-filtering on decoded video data. The post-filter comprises two independent processing units, one for horizontal deblocking and the other for vertical deblocking and deringing, each processing unit in communication with a memory system, which can include DRAM. The post-filter further comprises a local memory, which can be SRAM, for high speed access to data being processed by the vertical deblocking and deringing filter, without additional accesses to the memory system. Further, horizontal deblocking and vertical deblocking and deringing functions can be performed concurrently in a pipe-lined fashion.
    Type: Application
    Filed: May 13, 2003
    Publication date: November 18, 2004
    Inventor: Ren-Yuh Wang
  • Patent number: 6774943
    Abstract: An apparatus for edge enhancement of a digital image provided as raw digital image data to an input terminal and for providing processed image data to an output terminal. An offset processing circuit is coupled to the input terminal and configured to receive the raw data and generate offset data. An interpolation circuit is coupled to the offset processing circuit and configured to receive the offset data and to provide interpolated data. A color processing circuit is coupled to the interpolation circuit and configured to process the interpolated data to generate color data. An edge enhancement circuit is coupled to the interpolation circuit and the color processing circuit and configured to enhance the edges of the image based on the interpolated data and the color data to generate enhanced data. A lookup table is coupled to the color processing circuit and the edge enhancement circuit and configured to lookup the color data and the enhanced data to generate lookup data.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: August 10, 2004
    Assignee: ESS Technology, Inc.
    Inventors: Sophia Wei-Chun Kao, Der-Ren Chu, Ren-Yuh Wang
  • Patent number: 6765625
    Abstract: “An image processing system, in which bit shuffling is done in order to maintain image quality, stores digitized video data bits stream in a conventional memory, such as a DRAM. The image processing system is suitable for widely-used image compression standards that integrate various algorithms into a compression system, such as the standards specified in the Digital Video Standard (the DV-SD standard, or “Blue Book”). The image processing system receives a number of blocks associated with a first video frame and stores these blocks in the DRAM. The image processing system receives and stores blocks associated with a second video frame in the DRAM. The image processing system, processes the blocks of the first video frame while storing the blocks of the second video fame.
    Type: Grant
    Filed: June 16, 2000
    Date of Patent: July 20, 2004
    Assignee: Divio, Inc.
    Inventors: Wilbur W. Lee, Ren-Yuh Wang
  • Patent number: 6760888
    Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.
    Type: Grant
    Filed: November 1, 2002
    Date of Patent: July 6, 2004
    Assignee: Tensilica, Inc.
    Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Rui Wang, D{grave over (r)}or Eliezer Maydan
  • Publication number: 20040113504
    Abstract: A cylindrical magnet ring assembly having a cylinder magnet flux ring (102) formed with a plurality of inwardly projecting anchors (108); a plurality of permanent magnets (104), wherein the magnet can be formed with step portions (112) in the inner radial surface; a molded plastic member (106) being molded around the magnets and anchors to secure the magnets to a surface of the cylinder flux ring. There are several variations of the embodiments of the invention. Few embodiments are the following: in one aspect of the invention, magnets are inserted into magnet molded around an assembly ring (806) and the molded plastic secures the assembly ring to the flux ring; in another aspect, there are two assembly rings, a first assembly ring (is inserted into the one side of the cylinder flux ring then the second assembly ring is inserted into the other side of the cylinder flux ring and mated to the first assembly ring, after that the molded plastic secures the two assembly rings.
    Type: Application
    Filed: August 20, 2003
    Publication date: June 17, 2004
    Inventors: Michael Agnes, Allyn Boyce, Hung Du, Earl Ortt, Brandon Verbrugge, Richard T Walter, Ren H Wang, Jiaqi Zhang
  • Patent number: 6701515
    Abstract: In selecting and building a processor configuration, a user creates a new set of user-defined instructions, places them in a file directory, and invokes a tool that processes the user instructions and transforms them into a form usable by the software development tools. The user then invokes the software development tools, telling the tools to dynamically use the instructions created in the new directory. In this way, the user may customize a processor configuration by adding new instructions and within minutes, be able to evaluate that feature. The user is able to keep multiple sets of potential instructions and easily switch between them when evaluating their application.
    Type: Grant
    Filed: May 27, 1999
    Date of Patent: March 2, 2004
    Assignee: Tensilica, Inc.
    Inventors: Robert P. Wilson, Dror E. Maydan, Albert Ren-Rui Wang, Walter D. Lichtenstein, Weng Kiang Tjiang
  • Publication number: 20040020028
    Abstract: An armature for a brush commutated electric motor having a distributed coil winding arrangement for reducing brush arcing and electro-magnetic interference (EMI). The winding pattern involves segmenting each coil into first and second subcoil portions with differing pluralities of turns. Each subcoil portion is wound around separate pairs of spaced apart slots of a lamination stack. Adjacent coils are wound such that one subcoil portion of each is wound in a common slot to therefore form an overlapping arrangement of each pair of adjacently coils. The winding pattern serves to “shift” the resultant magnetic axes of each coil in such a manner so as to significantly reduce brush arcing and the EMI resulting therefrom. The reduction in EMI is sufficient to eliminate the need for EMI reducing components, such as chokes, which have typically been required to maintain EMI to acceptably low levels.
    Type: Application
    Filed: July 3, 2003
    Publication date: February 5, 2004
    Inventor: Ren Hong Wang
  • Publication number: 20040017124
    Abstract: An armature for a brush commutated electric motor having a distributed coil winding arrangement for reducing brush arcing and electromagnetic interference (EMI). The winding pattern involves segmenting each coil into first and second subcoil portions with differing pluralities of turns. Each subcoil portion is wound around separate pairs of spaced apart slots of a lamination stack. Adjacent coils are wound such that one subcoil portion of each is wound in a common slot to therefore form an overlapping arrangement of each pair of adjacently coils. The winding pattern serves to “shift” the resultant magnetic axes of each coil in such a manner so as to significantly reduce brush arcing and the EMI resulting therefrom. The reduction in EMI is sufficient to eliminate the need for EMI reducing components, such as chokes, which have typically been required to maintain EMI to acceptably low levels.
    Type: Application
    Filed: July 3, 2003
    Publication date: January 29, 2004
    Inventor: Ren Hong Wang
  • Publication number: 20030208723
    Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.
    Type: Application
    Filed: November 1, 2002
    Publication date: November 6, 2003
    Applicant: TENSILICA, INC.
    Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Rui Wang, Dror Eliezer Maydan
  • Patent number: 6614934
    Abstract: A method and apparatus for concatenating data words from a bitstream includes a scratch memory (802, 902) containing last words of unfinished blocks and left-aligned extra data words of finished blocks. A previous register (808, 908) holds one last word of an unfinished block. A next register (806, 906) holds a first of possibly many extra data words associated with the last word. A bit detector (810, 910), coupled to the previous register (808, 908) and the next register (806, 906), first concatenates the last word and the first extra data word and identifies selected bits for the detection of a valid code word. When no more valid code words can be found from the selected bits, and more data associated with the unfinished block exists, the first extra data word is moved to the previous register (808, 908) and a second extra data word is moved to the next register (806, 906). The first extra data word and the second extra data word are concatenated for the detection of another valid code word.
    Type: Grant
    Filed: March 27, 2000
    Date of Patent: September 2, 2003
    Assignee: Divio, Inc.
    Inventors: Tony H. Wu, Ren-Yuh Wang
  • Publication number: 20030159271
    Abstract: An armature for a brush commutated electric motor having a distributed coil winding arrangement for reducing brush arcing and electromagnetic interference (EMI). The winding pattern involves segmenting each coil into first and second subcoil portions with differing pluralities of turns. Each subcoil portion is wound around separate pairs of spaced apart slots of a lamination stack. Adjacent coils are wound such that one subcoil portion of each is wound in a common slot to therefore form an overlapping arrangement of each pair of adjacently coils. The winding pattern serves to “shift” the resultant magnetic axes of each coil in such a manner so as to significantly reduce brush arcing and the EMI resulting therefrom. The reduction in EMI is sufficient to eliminate the need for EMI reducing components, such as chokes, which have typically been required to maintain EMI to acceptably low levels.
    Type: Application
    Filed: April 1, 2003
    Publication date: August 28, 2003
    Inventor: Ren Hong Wang
  • Patent number: 6594398
    Abstract: New and improved methods and apparatus for run-length encoding video data. These techniques are especially suited to digital video applications, in which input to a video decoder is generated in order to determine run lengths and amplitudes. The implementations are suitable for widely-used image compression standards that integrate various algorithms into a compression system, such as the standards specified in the Digital Video Standard (the “Blue Book”).
    Type: Grant
    Filed: March 23, 2000
    Date of Patent: July 15, 2003
    Assignee: Divio, Inc.
    Inventors: Tony H. Wu, Ren-Yuh Wang
  • Patent number: 6566782
    Abstract: An armature for a brush commutated electric motor having a distributed coil winding arrangement for reducing brush arcing and electro-magnetic interference (EMI). The winding pattern involves segmenting each coil into first and second subcoil portions with differing pluralities of turns. Each subcoil portion is wound around separate pairs of spaced apart slots of a lamination stack. Adjacent coils are wound such that one subcoil portion of each is wound in a common slot to therefore form an overlapping arrangement of each pair of adjacently coils. The winding pattern serves to “shift” the resultant magnetic axes of each coil in such a manner so as to significantly reduce brush arcing and the EMI resulting therefrom. The reduction in EMI is sufficient to eliminate the need for EMI reducing components, such as chokes, which have typically been required to maintain EMI to acceptably low levels.
    Type: Grant
    Filed: June 14, 2000
    Date of Patent: May 20, 2003
    Assignee: Black & Decker Inc.
    Inventor: Ren Hong Wang
  • Patent number: 6516029
    Abstract: New and improved apparatus and methods for video encoding, for example, to efficiently and concurrently apply adaptive encoding techniques to convert analog data into digital formats, such as Digital Video (DV) format. A parallel system receives a block of video data and based on the computations and comparisons performed determines the best quantization factor for the block of video data. In an embodiment, the parallel system performs selected operations in parallel to save time and increase speed.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: February 4, 2003
    Assignee: Divio, Inc.
    Inventor: Ren-Yuh Wang
  • Patent number: 6515715
    Abstract: New and improved methods and apparatus for code packing in a digital video system. Among others, a method of transferring a data block to a storage device is disclosed. The storage device can include a plurality of compartments. The method includes receiving a plurality of length values. Each length value can correspond to a data block from a plurality of data blocks. The method further includes filling a first compartment of the storage device with a portion of data from a first data block, searching the length values to identify one of the plurality of data blocks having a length value less than a threshold value, and filling a second compartment with a remaining portion of the data from the first data block. In one embodiment, the second compartment can correspond to the identified data block.
    Type: Grant
    Filed: September 27, 1999
    Date of Patent: February 4, 2003
    Assignee: Divio, Inc.
    Inventors: Sophie Essen, Ren-Yuh Wang
  • Patent number: 6512852
    Abstract: New and improved methods and apparatus for concatenating data words from a bitstream. These techniques are especially suited to digital video applications, in which input to a video decoder is generated in order to determine run lengths and amplitudes. This implementation is suitable for widely-used image compression standards that integrate various algorithms into a compression system, such as the standards specified in the Digital Video Standard (the “Blue Book”).
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: January 28, 2003
    Assignee: Divio, Inc.
    Inventors: Tony H. Wu, Ren-Yuh Wang
  • Patent number: 6509932
    Abstract: A method and apparatus for providing audio in a digital video system. Equations for a value n are provided for replacement into the conventional audio data shuffling equations. The equations for the value n provide for simple, efficient techniques to, in turn, calculate values for track number (TK), block number (BK), and data position number (DP). The values TK, BK, DP can be used in an address generation scheme to generate a page value and an offset value. The page value and the offset value for a particular sample of digital audio data, in part, determine the location of the sample in a memory storing the digital audio data. The present invention can be implemented for both four channel and two channel modes under both the NTSC and the PAL standards in accordance with specifications set forth in the Digital Video Standard (the “Blue Book”).
    Type: Grant
    Filed: October 1, 1999
    Date of Patent: January 21, 2003
    Assignee: Divio, Inc.
    Inventors: Der-Ren Chu, Ren-Yuh Wang
  • Patent number: 6507673
    Abstract: New and improved apparatus and methods for video encoding, for example, to efficiently and concurrently encode video data into digital formats, such as Digital Video (DV) format. A pipelined system receives a block of video data and based on the computations and comparisons concurrently performed on the pixels within the block of video data determines which type of transformation is most appropriate for a given block of video data.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: January 14, 2003
    Assignee: Divio, Inc.
    Inventors: Ren-Yuh Wang, Yi-Yung Jeng
  • Patent number: 6477683
    Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.
    Type: Grant
    Filed: February 5, 1999
    Date of Patent: November 5, 2002
    Assignee: Tensilica, Inc.
    Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Rui Wang, Dror Eliezer Maydan
  • Patent number: 6477697
    Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. The standardized language is capable of handling instruction set extensions which modify processor state or use configurable processors. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.
    Type: Grant
    Filed: May 28, 1999
    Date of Patent: November 5, 2002
    Assignee: Tensilica, Inc.
    Inventors: Earl A. Killian, Richard Ruddell, Albert Ren-Rui Wang