Patents by Inventor Ren?an Wang

Ren?an Wang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100068465
    Abstract: A housing, comprising: a substrate; a paint coating formed on the substrate, the paint coating defining a plurality of through grooves therein; and a metal coating, the metal coating being formed in the through grooves. A method for making housing, comprising: providing a substrate; applying a paint coating on the substrate by spray painting; forming a plurality of through grooves on the paint coating by etching; and forming a metal coating in the through grooves by electroplating.
    Type: Application
    Filed: August 12, 2009
    Publication date: March 18, 2010
    Applicants: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (Hong Kong) LIMITED
    Inventors: JONG-YI SU, CHENG-SHIN CHEN, REN-NING WANG, YUAN-ZHU ZHOU
  • Publication number: 20100025256
    Abstract: A surface treatment method for housings comprising: providing a metal housing and pre-treating it to be cleaned; electroplating the housing to form a hexavalent chromium coating on the surface of the housing; and electroplating the housing to form a trivalent chromium coating on the hexavalent chromium coating.
    Type: Application
    Filed: July 17, 2009
    Publication date: February 4, 2010
    Applicants: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (HONG KONG) LIMITED
    Inventors: JONG-YI SU, CHENG-SHIN CHEN, REN-NING WANG, BIN LIU
  • Publication number: 20100025255
    Abstract: An electroplating method for magnesium and magnesium alloys, comprising: providing a magnesium or magnesium alloy substrate and pre-treating it to be cleaned; roughening the surface of the substrate; activating the surface of the substrate; chemically plating the substrate to form a nickel coating on its surface; and electroplating the substrate to form, in order, a first nickel coating, a copper coating, a second nickel coating, and a chromium coating on the chemically produced nickel coating.
    Type: Application
    Filed: July 7, 2009
    Publication date: February 4, 2010
    Applicants: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (HONG KONG) LIMITED
    Inventors: JONG-YI SU, CHENG-SHIN CHEN, REN-NING WANG, HONG-JUN QU
  • Publication number: 20090321267
    Abstract: A method for surface treating plastic products is provided. The method includes the steps of providing a plastic substrate, the plastic substrate being made of electroplatable material; forming at least one electroconductive coating on the plastic substrate surface by electro-less plating; forming a copper layer on the electroconductive coating by electroplating; partially etching the surface of the copper layer using a laser to form a rough area; and forming a top coating on the copper layer by electroplating. Both shiny appearance and dusky appearance of the plastic substrate can be present by this method.
    Type: Application
    Filed: December 12, 2008
    Publication date: December 31, 2009
    Applicants: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (Hong Kong) LIMITED
    Inventors: JONG-YI SU, CHENG-SHIN CHEN, REN-NING WANG, YUN-CHEN MAO, ZHI-FENG LIN
  • Publication number: 20090255823
    Abstract: A method for electroplating a plastic substrate includes the following steps, a plastic substrate is firstly provided. The plastic substrate is then pretreated to form a noble metal coating. The noble metal coating is coated with a copper coating. A first chrome coating is electroplated onto the copper coating using a first electrolyte including a chromic component. A second chrome coating is electroplated onto the first chrome coating using a second electrolyte including a chromyl component.
    Type: Application
    Filed: April 1, 2009
    Publication date: October 15, 2009
    Applicants: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (HONG KONG) LIMITED
    Inventors: JONG-YI SU, CHENG-SHIN CHEN, REN-NING WANG
  • Publication number: 20090255824
    Abstract: A method for surface treating a substrate includes following steps. Firstly, a substrate including a metallic surface capable of being electroplated with a metal coating is provided. Secondly, a first metal coating is electroplated onto the metallic surface of the substrate. Thirdly, an oxidized metal film is formed to cover the first metal coating. The first metal coating of substrate is blasted using quartz sand. The oxidized metal film is removed from the first metal coating. The second metal coating is electroplated onto the first metal coating.
    Type: Application
    Filed: April 1, 2009
    Publication date: October 15, 2009
    Applicants: SHENZHEN FUTAIHONG PRECISION INDUSTRY CO., LTD., FIH (HONG KONG) LIMITED
    Inventors: JONG-YI SU, CHENG-SHIN CHEN, YUEH-FENG LEE, CHUAN-LONG CHEN, REN-NING WANG, RUN-YI CHEN
  • Patent number: 7597794
    Abstract: The present invention is a separation method and system in which granulation of coupled post-extraction asphalt residue is used to achieve deep separation of heavy oil. A dispersion solvent is introduced into the asphalt phase after separation by solvent extraction and the asphalt phase undergoes rapid phase change in a gas-solid separator and is dispersed into solid particles while the solvent vaporizes, resulting in low temperature separation of asphalt and solvent with adjustable size of the asphalt particles. The separation method of this invention also includes a three-stage separation of heavy oil feedstock, in which the deasphalted oil phase separated from heavy oil is treated with supercritical solvent and results in the further separation of the resin portion of the deasphalted oil, maximizing the yield and quality of the deasphalted oil.
    Type: Grant
    Filed: November 1, 2005
    Date of Patent: October 6, 2009
    Inventors: Suoqi Zhao, Chunming Xu, Ren′an Wang, Zhiming Xu, Xuewen Sun, Keng H. Chung
  • Publication number: 20090177876
    Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.
    Type: Application
    Filed: October 9, 2008
    Publication date: July 9, 2009
    Inventors: Albert Ren-Rui WANG, Richard Ruddell, David William Goodwin, Earl A. Killian, Nupur Bhattacharyya, Marines Puig Medina, Walter David Lichtenstein, Pavlos Konas, Rangarajan Srinivasan, Christopher Mark Songer, Akilesh Parameswar, Dror E. Maydan, Ricardo E. Gonzalez
  • Publication number: 20090175342
    Abstract: Methods and systems for image processing are provided. A particular method includes receiving a video object plane (VOP) at an image processing device and decoding the received VOP. The method also includes storing an order number of the decoded VOP at a P-VOP queue in a memory of the image processing device when the received VOP is a predictive coded VOP (P-VOP). The method further includes storing the order number of the decoded VOP at a first available location of a display ordered read queue in the memory of the image processing device when the received VOP is not a P-VOP.
    Type: Application
    Filed: March 18, 2009
    Publication date: July 9, 2009
    Applicant: SigmaTel, LLC (formerly known as SigmaTel, Inc.)
    Inventors: Chin-Long Lin, Ren-Yuh Wang
  • Publication number: 20090172630
    Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.
    Type: Application
    Filed: October 9, 2008
    Publication date: July 2, 2009
    Inventors: Albert Ren-Rui Wang, Richard Ruddell, David William Goodwin, Earl A. Killian, Nupur Bhattacharyya, Marines Puig Medina, Walter David Lichtenstein, Pavlos Konas, Rangarajan Srinivasan, Christopher Mark Songer, Akilesh Parameswar, Dror E. Maydan, Ricardo E. Gonzalez
  • Publication number: 20090125866
    Abstract: A method for decomposing a target pattern containing features to be printed on a wafer into multiple patterns. The method includes the steps of segmenting the target pattern into a plurality of patches; identifying critical features within each patch which violate minimum spacing requirements; generating a critical group graph for each of the plurality of patches having critical features, where the critical group graph of a given patch defines a coloring scheme of the critical features within the given patch, and the critical group graph identifies critical features extending into adjacent patches to the given patch; generating a global critical group graph for the target pattern, where the global critical group graph includes the critical group graphs of each of the plurality of patches, and an identification of the features extending into adjacent patches; and coloring the target pattern based on the coloring scheme defined by the global critical group graph.
    Type: Application
    Filed: November 13, 2008
    Publication date: May 14, 2009
    Inventors: ALBERT REN-RUI WANG, RICHARD RUDDELL, DAVID WILLIAM GOODWIN, EARL A. KILLIAM, NUPUR BHATTACHARYYA, MARINES PUIG MEDINA, WALTER DAVID LICHTENSTEIN, PAVLOS KONAS, RANGARAJAN SRINIVASAN, CHRISTOPHER MARK SONGER, AKILESH PARAMESWAR, DROR E. MAYDAN, RICARDO E. GONZALEZ
  • Publication number: 20090021090
    Abstract: A power tool has a motor having a stator made by separately forming pole pieces, return path pieces and field coils. The field coils are placed over necks of the pole path pieces and the return path pieces are affixed to the pole pieces. An armature having an outside diameter of at least 0.625 the outside diameter of the stator is placed in the stator. The field coils may be formed so that they extend beyond pole tips of the pole pieces.
    Type: Application
    Filed: March 6, 2006
    Publication date: January 22, 2009
    Applicant: BLACK AND DECKER INC.
    Inventors: Hung T. Du, Earl M. Ortt, Brandon L. Verbrugge, Garrett P. McCormick, Michael A. Zemlock, Eric J. Samuelsen, Kevin M. Hogan, Jiaqi Zhang, Ren Hong Wang, Frank A. Mannarino, Allison A. Smith, Spencer G. Maid, Therese M. Rakosky, Kyle J. Wheaton, Antonios M. Nicolaidis, Shane Ashley Moll, James C. Benton, Eric L. Bernstein
  • Patent number: 7437700
    Abstract: A system for generating processor hardware supports a language for significant extensions to the processor instruction set, where the designer specifies only the semantics of the new instructions and the system generates other logic. The extension language provides for the addition of processor state, including register files, and instructions that operate on that state. The language also provides for new data types to be added to the compiler to represent the state added. It allows separate specification of reference semantics and instruction implementation, and uses this to automate design verification. In addition, the system generates formatted instruction set documentation from the language specification.
    Type: Grant
    Filed: November 16, 2005
    Date of Patent: October 14, 2008
    Assignee: Tensilica, Inc.
    Inventors: Albert Ren-Rui Wang, Richard Ruddell, David William Goodwin, Earl A. Killian, Nupur Bhattacharyya, Marines Puig Medina, Walter David Lichtenstein, Pavlos Konas, Rangarajan Srinivasan, Christopher Mark Songer, Akilesh Parameswar, Dror E. Maydan, Ricardo E. Gonzalez
  • Publication number: 20080244506
    Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.
    Type: Application
    Filed: June 9, 2008
    Publication date: October 2, 2008
    Inventors: Earl A. Killian, Richardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Ru Wang, Dror Eliezer Maydan
  • Publication number: 20080244471
    Abstract: An automated processor design tool uses a description of customized processor instruction set extensions in a standardized language to develop a configurable definition of a target instruction set, a Hardware Description Language description of circuitry necessary to implement the instruction set, and development tools such as a compiler, assembler, debugger and simulator which can be used to develop applications for the processor and to verify it. Implementation of the processor circuitry can be optimized for various criteria such as area, power consumption, speed and the like. Once a processor configuration is developed, it can be tested and inputs to the system modified to iteratively optimize the processor implementation. By providing a constrained domain of extensions and optimizations, the process can be automated to a high degree, thereby facilitating fast and reliable development.
    Type: Application
    Filed: June 9, 2008
    Publication date: October 2, 2008
    Inventors: Earl A. Killian, Ricardo E. Gonzalez, Ashish B. Dixit, Monica Lam, Walter D. Lichtenstein, Christopher Rowen, John C. Ruttenberg, Robert P. Wilson, Albert Ren-Rui Wang, Dror Eliezer Maydan
  • Patent number: 7424056
    Abstract: A device and a method are disclosed for motion estimation and bandwidth reduction in a memory. The device includes a memory for storing a plurality of frame data, a controller connected to the memory, a first motion estimation processor for performing a coarse-tuning operation and a second motion estimation processor for performing a fine-tuning operation. Similarity between a reference frame and a current frame is calculated based on the averages of every two adjacent pixels in the reference macroblocks and current macroblocks. The amount of calculations for determining motion estimation is greatly reduced, and bandwidth in utilizing the memory is accordingly reduced as motion estimation is advantageously achieved.
    Type: Grant
    Filed: July 4, 2003
    Date of Patent: September 9, 2008
    Assignee: SIGMATEL, Inc.
    Inventors: Chin-Long Lin, Ren-Yuh Wang
  • Patent number: 7362810
    Abstract: An implementation of an MPEG-4 compliant post-filter for image data, which performs deblocking and deringing post-filtering on decoded video data. The post-filter comprises two independent processing units, one for horizontal deblocking and the other for vertical deblocking and deringing, each processing unit in communication with a memory system, which can include DRAM. The post-filter further comprises a local memory, which can be SRAM, for high speed access to data being processed by the vertical deblocking and deringing filter, without additional accesses to the memory system. Further, horizontal deblocking and vertical deblocking and deringing functions can be performed concurrently in a pipe-lined fashion.
    Type: Grant
    Filed: May 13, 2003
    Date of Patent: April 22, 2008
    Assignee: Sigmatel, Inc.
    Inventor: Ren-Yuh Wang
  • Publication number: 20070267990
    Abstract: A power tool may include an electronically commutated motor such as, for example, a brushless DC permanent magnet motor with a rotor having internally mounted magnets and/or cavities filled with air or other non-magnetic materials. A control system may be used to control the motor in a manner that implements field weakening when the speed of the motor increases beyond its rated motor speed, or when the torque demands on the motor continue to increase after the maximum power output of the motor is reached. The field weakening may offset the growing back EMF and may enable a constant power and constant efficiency to be achieved by the motor over a wide speed range, rather than at just a single predetermined operating speed. Pulse width modulation control of the motor may be used up until the motor reaches its maximum power output.
    Type: Application
    Filed: May 22, 2007
    Publication date: November 22, 2007
    Applicant: BLACK & DECKER INC.
    Inventors: Mehdi Abolhassani, Shailesh P. Waikar, Ren H. Wang, Uday S. Deshpande
  • Patent number: 7284080
    Abstract: The invention provides a system and method for memory bus assignment for a plurality of functional devices. According to a preferred embodiment, the invention provides a system comprising a plurality of functional devices accessing a memory bus wherein the memory bus allows access by one of the functional devices for one cycle of period of time, a plurality of request agents corresponding to the functional devices, a control register respectively storing access priority grades for the request agents, a plurality of counter timers respectively loading the access priority grades; and a bus elector coupled with the counter timers wherein the bus elector respectively compares the loaded access priority grades and elects one out of the request agents according to the compared access priority grades. The memory bus accordingly allows access by one of the functional devices corresponding to the elected request agent for one cycle of period of time.
    Type: Grant
    Filed: July 4, 2003
    Date of Patent: October 16, 2007
    Assignee: Sigmatel, Inc.
    Inventors: Chin-Long Lin, Ren-Yuh Wang
  • Patent number: 7274126
    Abstract: An armature for a brush commutated electric motor having a distributed coil winding arrangement for reducing brush arcing and electromagnetic interference (EMI). The winding pattern involves winding a first coil into a first pair of slots of the armature. A second coil having a first subcoil portion is then wound into the same slots as the first coil, while a second subcoil portion of the second coil is wound into a pair of slots that is offset by one slot position from the first pair of slots. The two subcoil portions have the same number of turns, and the total turns of the two subcoil portions equals the number of turns of the first coil. A third coil is then wound in the same slots as the second subcoil portion of the second coil. The third coil has the same number of turns as the first coil. This pattern is repeated around the armature.
    Type: Grant
    Filed: September 8, 2004
    Date of Patent: September 25, 2007
    Assignee: Black & Decker Inc.
    Inventors: Richard T. Walter, Ren Hong Wang