Abstract: A nonvolatile memory cell includes a semiconductor substrate, a first OD region, a second OD region for forming an erase gate region, and a trench isolation region separating the first OD region from the second OD region. A select transistor is disposed on the first OD region. A floating gate transistor is serially connected to the select transistor and is disposed on the first OD region. The floating gate transistor comprises a floating gate overlying the first OD region. A floating gate extension continuously extends from the floating gate to the second OD region. A shallow junction diffusion region is situated directly under the floating gate extension within the second OD region.

Abstract: A luminaire includes at least a cover and a mounting plate. The mounting plate includes one or more vertical protrusions and one or more horizontal protrusions that are substantially perpendicular to each other. Further, the mounting plate includes a tab that is substantially perpendicular to the one or more horizontal protrusions. The cover includes a pair of top apertures and a tab aperture. During installation of the luminaire, the cover is hung from the mounting plate by inserting each horizontal protrusion of the mounting plate through the respective top aperture of the cover. Alternatively, the cover is hung from the mounting plate by inserting the tab of the mounting plate through the tab aperture of the cover. After installation, the cover may be secured to the mounting plate by inserting the pair of vertical protrusions of the mounting plate through the pair of top apertures of the cover.

Abstract: A voltage level shift circuit comprises a first pair of transistors and a second pair of transistors. A first transistor of the second pair of transistors is coupled with an input signal terminal. A second transistor of the transistors of the second pair of transistors is coupled with an inverted input signal terminal. The transistors of the second pair of transistors are cross-coupled with the transistors of the first pair of transistors. The voltage level shift circuit also comprises a third pair of transistors. The transistors of the third pair of transistors are coupled with the transistors of the first pair of transistors and the transistors of the second pair of transistors. A first transistor of the third pair of transistors is directly coupled with an output signal terminal and second transistor of the third pair of transistors is directly coupled with an inverted output signal terminal.

Abstract: A pharmacological composition for use in inhibiting differentiation, functional activities, and population of granulo-cytic myeloid-derived suppressor cells (gMDSCs) and/or suppressing, tumor metastasis in a subject in need thereof is disclosed. The composition comprises a therapeutically effective amount of Bidens pilosa extract, or more than one polyacetylenic compounds purified or isolated from the B. pilosa extract, and a pharmaceutically acceptable carrier.

Abstract: A semiconductor device structure is provided. The semiconductor device structure includes a substrate. The semiconductor device structure includes a gate stack over the substrate. The gate stack has a first upper portion and a first lower portion, and the first upper portion is wider than the first lower portion. The semiconductor device structure includes a spacer layer surrounding the gate stack. The spacer layer has a second upper portion and a second lower portion. The second upper portion is thinner than the second lower portion.

Abstract: A display driving apparatus including a lightness adjusting unit, a gamma adjusting unit, a pre-charging voltage adjusting unit and a source driving unit is disclosed. The lightness adjusting unit receives and adjusts a lightness of an image data. The gamma adjusting unit adjusts a gamma voltage corresponding to the image data to generate a source data voltage. The pre-charging voltage adjusting unit calculates a highest data voltage and a lowest data voltage which can be outputted by a source electrode and adjusts a pre-charging voltage accordingly to make the adjusted pre-charging voltage the same with the highest data voltage or the lowest data voltage or only a shifted voltage different from the highest data voltage or the lowest data voltage of the image data. The source driving unit outputs the adjusted pre-charging voltage and the source data voltage to a display panel respectively.

Abstract: A method includes: mixing a polymer cement and a filler to form a solution masterbatch; optionally drying the solution masterbatch to form a crumb polymer composition; mixing a low viscosity polymeric or oligomeric liquid into the solution masterbatch or crumb polymer composition; and intermeshing mixing the solution masterbatch or crumb polymer composition.

Abstract: A memory cell includes a program select transistor, a program element, a read select transistor, a read element, and an erase element. The program select transistor is coupled to a program source line, a program select line, and a program control line. The program element is coupled to the second terminal of the program select transistor, a program bit line, and the program control line. The read select transistor is coupled to a read source line, a read select line, and a bias control line. The read element is coupled to the second terminal of the read select transistor, a read bit line, and the bias control line. The erase element is coupled to an erase control line. A floating gate is coupled to the erase element, the program element and the read element.

Abstract: A non-volatile memory cell includes a substrate, a select gate, a floating gate, and an assistant control gate. The substrate includes a first diffusion region, a second diffusion region, a third diffusion region, and a fourth diffusion region. The select gate is formed above the first diffusion region and the second diffusion region in a polysilicon layer. The floating gate is formed above the second diffusion region, the third diffusion region and the fourth diffusion region in the polysilicon layer. The assistant control gate is formed above the floating gate in a metal layer, wherein an area of the assistant control gate overlaps with at least half an area of the floating gate.

Abstract: An erasable programmable non-volatile memory includes a first transistor, a second transistor, an erase gate region and a metal layer. The first transistor includes a select gate, a first doped region and a second doped region. The select gate is connected with a word line. The first doped region is connected with a source line. The second transistor includes the second doped region, a third doped region and a floating gate. The third doped region is connected with a bit line. The erase gate region is connected with an erase line. The floating gate is extended over the erase gate region and located near the erase gate region. The metal layer is disposed over the floating gate and connected with the bit line.

Abstract: The present invention relates to a method for treating Alzheimer's disease and 2,3-BPG metabolic disorder induced morbidities, comprising administrating a phthalide compound to an Alzheimer's disease patient or a patient having 2,3-BPG metabolic disorder induced morbidities, wherein the method is characterized by that the phthalide compound has the same effect as 2,3-BPG on modulating hemoglobin to reduce its oxygen affinity and can thus act as a 2,3-BPG functional substitute when the 2,3-BPG concentration is too low in the Alzheimer's disease patient or in the patient having 2,3-BPG metabolic disorder induced morbidities to maintain the normal oxygen release function of hemoglobin and therefore to maintain the normal cellular oxygenation level.

Abstract: The present invention relates to a method for substituting for or acting with the hyperbaric oxygen therapy to improve hypoxia, comprising the step of: administrating a phthalide compound to a subject in need thereof, wherein the phthalide compound can increase the oxygen release efficiency of blood hemoglobin (Hb) in the subject and further increase the cellular oxygenation level, and when the phthalide compound substitutes for or act with the hyperbaric oxygen therapy, the common adverse side effects of the hyperbaric oxygen therapy, such as barotrauma, decompression sickness and oxygen poisoning, are prevented. The phthalide compound is used to substitute for or act with 2,3-BPG, to modulate and decrease the oxygen affinity of hemoglobin (Hb), to increase the oxygen release efficiency of hemoglobin (Hb) to tissue cells, thereby achieving a normal cellular oxygenation level and maintaining the cellular oxygenation level in a normal range.

Abstract: The present invention relates to a method for preventing cancer by using a phthalide compound, wherein the phthalide compound has an effect of increasing the oxygen release efficiency of hemoglobin (Hb) of a subject to increase the oxygenation level of organs and tissue cells, thereby preventing the cellular oxygenation level against falling below the critical cellular oxygen requirements under which the normal cells can turn cancerous. Although cancer may be caused by a variety of reasons, including congenital inheritance, external environment, air pollution or poor living and dietary habits, there is only one primary and common reason in causing cancers, the excessively low cellular oxygenation level. When the oxygenation level of any cell falls below 60% of its physiological oxygen requirements, the normal cell may turn cancerous.

Abstract: Provided is a material composition and method for that includes providing a substrate and forming a resist layer over the substrate. In various embodiments, the resist layer includes a multi-metal complex including an extreme ultraviolet (EUV) absorption element and a bridging element. By way of example, the EUV absorption element includes a first metal type and the bridging element includes a second metal type. In some embodiments, an exposure process is performed to the resist layer. After performing the exposure process, the exposed resist layer is developed to form a patterned resist layer.

Abstract: A method and a system for integrating multiple camera images to track a vehicle are provided. In the method, a security request of a vehicle to be tracked is received from a user, in which the security request comprises registration information and position information of the vehicle. Next, images captured by multiple cameras in a specific range around a location of the position information are retrieved. The retrieved images are analyzed according to the registration information, so as to recognize the images comprising the vehicle. Finally, a message is issued when the images comprising the vehicle are recognized.

Abstract: The present invention provides a method of fabricating a fin field effect transistor (finFET), comprising: firstly, an interfacial layer is formed on a fin structure, next, a high-k dielectric layer is formed on the interfacial layer; afterwards, a stress film is formed on the high-k dielectric layer, an annealing process is then performed to the stress film, and an etching process is performed to remove the stress film.

Abstract: The present invention relates to a method for increasing the oxygen release efficiency of a hemoglobin-based blood substitute by using a phthalide compound, comprising the steps of: administering to a subject in need thereof the phthalide compound or co-administering to the subject in need thereof the phthalide compound along with the hemoglobin-based blood substitute, wherein the phthalide compound has an effect of increasing the oxygen release efficiency of the hemoglobin-based blood substitute, wherein the hemoglobin-based blood substitute can be fetal hemoglobin (HbF) or other Hb variants retaining two native ? subunits. The phthalide compound is used to substitute for or cooperate with 2,3-BPG, to play a role of a 2,3-BPG substitute, to act on the hemoglobin-based blood substitute to effectively substitute the function of normal hemoglobin in releasing oxygen to tissue cells, in order to maintain the cellular oxygenation level within a normal range.

Abstract: A single-poly nonvolatile memory cell includes an SOI substrate having a semiconductor layer, a first OD region and a second OD region on the semiconductor layer, an isolation region separating the first OD region from the second OD region, a PMOS select transistor disposed on the first OD region, and a PMOS floating gate transistor disposed on the first OD region. The PMOS floating gate transistor is serially connected to the PMOS select transistor. The PMOS floating gate transistor comprises a floating gate overlying the first OD region. A floating gate extension is continuously extended from the floating gate to the second OD region and is capacitively coupled to the second OD region.

Abstract: A nonvolatile memory structure includes a first PMOS transistor and a first floating-gate transistor on a first active region in a substrate, a second PMOS transistor and a second floating-gate transistor on a second active region in the substrate, and an n-type erase region in the substrate. A source line connects with sources of the first and the second PMOS transistors. A bit line connects with drains of the first and the second floating-gate transistors. A word line connects with first and the second select gates in the first and the second PMOS transistors respectively. An erase line connects with the n-type erase region. The first floating-gate transistor includes a first floating gate with an extended portion extending on a first portion of the n-type erase region. The second floating-gate transistor includes a second floating gate with an extended portion extending on a second portion of the n-type erase region.

Abstract: A memory cell includes a program select transistor, a program element, a read select transistor, a read element, and an erase element. The program select transistor is coupled to a program source line, a program select line, and a program control line. The program element is coupled to the second terminal of the program select transistor, a program bit line, and the program control line. The read select transistor is coupled to a read source line, a read select line, and a bias control line. The read element is coupled to the second terminal of the read select transistor, a read bit line, and the bias control line. The erase element is coupled to an erase control line. A floating gate is coupled to the erase element, the program element and the read element.