Abstract: A method of fabricating a semiconductor structure includes: providing a first wafer; providing a second wafer having a first surface and a second surface opposite to the first surface; contacting the first surface of the second wafer with the first wafer; and forming a plurality of scribe lines on the second surface of the second wafer, wherein the formation of the plurality of scribe lines includes removing portions of the second wafer from the second surface towards the first surface to form a third surface between the first surface and the second surface, and the plurality of scribe lines protrudes from the third surface of the second wafer.

Abstract: Introduced here are computer programs and associated computer-implemented techniques for deriving insights into the health of patients through analysis of audio data generated by electronic stethoscope systems. A diagnostic platform may be responsible for examining the audio data generated by an electronic stethoscope system so as to gain insights into the health of a patient. The diagnostic platform may employ heuristics, algorithms, or models that rely on machine learning or artificial intelligence to perform auscultation in a manner that significantly outperforms traditional approaches that rely on visual analysis by a healthcare professional.

Abstract: An integrated semiconductor device for manipulating and processing bio-entity samples and methods are described. The device includes a lower substrate, at least one optical signal conduit disposed on the lower substrate, at least one cap bonding pad disposed on the lower substrate, a cap configured to form a capped area, and disposed on the at least one cap bonding pad, a fluidic channel, wherein a first side of the fluidic channel is formed on the lower substrate and a second side of the fluidic channel is formed on the cap, a photosensor array coupled to sensor control circuitry, and logic circuitry coupled to the fluidic control circuitry, and the sensor control circuitry.

Abstract: A bioFET device includes a semiconductor substrate having a first surface and an opposite, parallel second surface and a plurality of bioFET sensors on the semiconductor substrate. Each of the bioFET sensors includes a gate formed on the first surface of the semiconductor substrate and a channel region formed within the semiconductor substrate beneath the gate and between source/drain (S/D) regions in the semiconductor substrate. The channel region includes a portion of the second surface of the semiconductor substrate. An isolation layer is disposed on the second surface of the semiconductor substrate. The isolation layer has an opening positioned over the channel region of more than one bioFET sensor of the plurality of bioFET sensors. An interface layer is disposed on the channel region of the more than one bioFET sensor in the opening.

Abstract: A server chassis includes a baseboard, a power distribution board, and a busbar module. The baseboard includes a front end and a rear end. The front end and the rear end define a chassis depth. The power distribution board is positioned on the baseboard. The busbar module includes a chassis-side busbar connector. The chassis-side busbar connector is configured to mate with a rack-side busbar connector. The rack-side busbar connector is positioned on a rack having a rack depth. The busbar module is adjustable, such that the chassis-side busbar connector mates with the rack-side busbar connector in a first configuration and a second configuration. In the first configuration, the rack depth is approximately equal to the chassis depth. In the second configuration, the rack depth is greater than the chassis depth.

Abstract: A method for manufacturing a semiconductor structure is provided. The method may include several operations. A piezoelectric capacitor is formed over a substrate, wherein the piezoelectric capacitor includes a metal electrode. An intermediate layer is formed on the metal electrode, and is patterned using a first mask layer as a mask. A metal layer is formed on the intermediate layer, wherein the metal layer electrically connects to the metal electrode. The metal layer is patterned using a second mask layer, wherein the intermediate layer is within a coverage area of the metal layer from a top-view perspective after the patterning of the metal layer. A semiconductor structure thereof is also provided.

Abstract: The present disclosure relates to an integrated chip structure. The integrated chip structure includes a dielectric stack disposed on a substrate. The integrated chip structure further includes one or more piezoelectric ultrasonic transducers (PMUTs) and one or more capacitive ultrasonic transducers (CMUTs). The one or more PMUTs include a piezoelectric stack disposed within the dielectric stack over one or more PMUT cavities. The one or more CMUTs include electrodes disposed within the dielectric stack and separated by one or more CMUT cavities. An isolation chamber is arranged within the dielectric stack laterally between the one or more PMUTs and the one or more CMUTs. The isolation chamber vertically extends past at least a part of both the one or more PMUTs and the one or more CMUTs.

Abstract: A biochip including a fluidic substrate having an opening extending completely through the fluidic substrate. The biochip further includes a silicon oxide coating on the fluidic substrate. The biochip further includes a plurality of sidewalls on the fluidic substrate, wherein the plurality of sidewalls defines a channel in fluid communication with the opening, the silicon oxide coating is between adjacent sidewalls of the plurality of sidewalls, and each of the plurality of sidewalls comprises polydimethylsiloxane (PDMS). The biochip further includes a detection substrate spaced from the fluidic substrate.

Abstract: A method of fabricating a semiconductor structure includes: providing a first wafer; providing a second wafer having a first surface and a second surface opposite to the first surface; contacting the first surface of the second wafer with the first wafer; and forming a plurality of scribe lines on the second surface of the second wafer, wherein the formation of the plurality of scribe lines includes removing portions of the second wafer from the second surface towards the first surface to form a third surface between the first surface and the second surface, and the plurality of scribe lines protrudes from the third surface of the second wafer.

Abstract: A sensor array includes a semiconductor substrate, a first plurality of FET sensors and a second plurality of FET sensors. Each of the FET sensors includes a channel region between a source and a drain region in the semiconductor substrate and underlying a gate structure disposed on a first side of the channel region, and a dielectric layer disposed on a second side of the channel region opposite from the first side of the channel region. A first plurality of capture reagents is coupled to the dielectric layer over the channel region of the first plurality of FET sensors, and a second plurality of capture reagents is coupled to the dielectric layer over the channel region of the second plurality of FET sensors. The second plurality of capture reagents is different from the first plurality of capture reagents.

Abstract: In some embodiments, a piezoelectric device is provided. The piezoelectric device includes a semiconductor substrate. A first electrode is disposed over the semiconductor substrate. A piezoelectric structure is disposed on the first electrode. A second electrode is disposed on the piezoelectric structure. A heating element is disposed over the semiconductor substrate. The heating element is configured to heat the piezoelectric structure to a recovery temperature for a period of time, where heating the piezoelectric structure to the recovery temperature for the period of time improves a degraded electrical property of the piezoelectric device.

Abstract: A server chassis includes a baseboard, a power distribution board, and a busbar module. The baseboard includes a front end and a rear end. The front end and the rear end define a chassis depth. The power distribution board is positioned on the baseboard. The busbar module includes a chassis-side busbar connector. The chassis-side busbar connector is configured to mate with a rack-side busbar connector. The rack-side busbar connector is positioned on a rack having a rack depth. The busbar module is adjustable, such that the chassis-side busbar connector mates with the rack-side busbar connector in a first configuration and a second configuration. In the first configuration, the rack depth is approximately equal to the chassis depth. In the second configuration, the rack depth is greater than the chassis depth.

Abstract: A semiconductor structure includes a first die, a second die, and an inter die via (IDV). The first die includes an interconnection structure and a CMOS device electrically connected to the interconnection structure. The second die includes a memory element including a first electrode, a ferroelectric layer on the first electrode, and a second electrode on the ferroelectric layer, wherein a peripheral region of the ferroelectric layer is exposed by and surrounding the second electrode from a top view perspective. The IDV electrically connects the interconnection structure of the first die to the memory element of the second die.

Abstract: A method of manufacturing a semiconductor structure includes following operations. A first substrate is provided. A plate is formed over the first substrate. The plate includes a first tensile member, a second tensile member, a semiconductive member between the first tensile member and the second tensile member, and a plurality of apertures penetrating the first tensile member, the semiconductive member and the second tensile member. A membrane is formed over and separated from the plate. The membrane include a plurality of holes. A plurality of conductive plugs passing through the plate or membrane are formed. A plurality of semiconductive pads are formed over the plurality of conductive plugs. The plate is bonded to a second substrate. The second substrate includes a plurality of bond pads, and the semiconductive pads are in contact with the bond pads.

Abstract: A method includes mounting an integrated electro-microfluidic probe card to a device area on a bio-sensor device wafer, wherein the electro-microfluidic probe card has a first major surface and a second major surface opposite the first major surface. The method further includes electrically connecting at least one electronic probe tip extending from the first major surface to a corresponding conductive area of the device area. The method further includes stamping a test fluid onto the device area. The method further includes measuring via the at least one electronic probe tip a first electrical property of one or more bio-FETs of the device area based on the test fluid.

Abstract: An integrated semiconductor device for manipulating and processing bio-entity samples and methods are described. The device includes a lower substrate, at least one optical signal conduit disposed on the lower substrate, at least one cap bonding pad disposed on the lower substrate, a cap configured to form a capped area, and disposed on the at least one cap bonding pad, a fluidic channel, wherein a first side of the fluidic channel is formed on the lower substrate and a second side of the fluidic channel is formed on the cap, a photosensor array coupled to sensor control circuitry, and logic circuitry coupled to the fluidic control circuitry, and the sensor control circuitry.

Abstract: A sensor array includes a semiconductor substrate, a first plurality of FET sensors and a second plurality of FET sensors. Each of the FET sensors includes a channel region between a source and a drain region in the semiconductor substrate and underlying a gate structure disposed on a first side of the channel region, and a dielectric layer disposed on a second side of the channel region opposite from the first side of the channel region. A first plurality of capture reagents is coupled to the dielectric layer over the channel region of the first plurality of FET sensors, and a second plurality of capture reagents is coupled to the dielectric layer over the channel region of the second plurality of FET sensors. The second plurality of capture reagents is different from the first plurality of capture reagents.

Abstract: A server chassis includes a baseboard, a power distribution board, and a busbar module. The baseboard includes a front end and a rear end. The front end and the rear end define a chassis depth. The power distribution board is positioned on the baseboard. The busbar module includes a chassis-side busbar connector. The chassis-side busbar connector is configured to mate with a rack-side busbar connector. The rack-side busbar connector is positioned on a rack having a rack depth. The busbar module is adjustable, such that the chassis-side busbar connector mates with the rack-side busbar connector in a first configuration and a second configuration. In the first configuration, the rack depth is approximately equal to the chassis depth. In the second configuration, the rack depth is greater than the chassis depth.

Abstract: The present disclosure provides a bio-field effect transistor (BioFET) and a method of fabricating a BioFET device. The method includes forming a BioFET using one or more process steps compatible with or typical to a complementary metal-oxide-semiconductor (CMOS) process. The BioFET device may include a substrate; a gate structure disposed on a first surface of the substrate and an interface layer formed on the second surface of the substrate. The interface layer may allow for a receptor to be placed on the interface layer to detect the presence of a biomolecule or bio-entity.

Abstract: Introduced here are computer programs and associated computer-implemented techniques for deriving insights into the health of patients through analysis of audio data generated by electronic stethoscope systems. A diagnostic platform may be responsible for examining the audio data generated by an electronic stethoscope system so as to gain insights into the health of a patient. The diagnostic platform may employ heuristics, algorithms, or models that rely on machine learning or artificial intelligence to perform auscultation in a manner that significantly outperforms traditional approaches that rely on visual analysis by a healthcare professional.