Patents by Inventor Ren-Dou Lee
Ren-Dou Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11851325Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.Type: GrantFiled: November 26, 2019Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Wei Chang, Ya-Jen Sheuh, Ren-Dou Lee, Yi-Chih Chang, Yi-Hsun Chiu, Yuan-Hsin Chi
-
Patent number: 11850702Abstract: In some embodiments, the present disclosure relates to a chemical mechanical planarization (CMP) tool. The CMP tool includes a carrier and a malleable membrane coupled to the carrier and having a lower surface facing away from the carrier. The lower surface of the malleable membrane includes a first malleable material within a central region of the lower surface and a second malleable material within a peripheral region of the lower surface, which surrounds the central region. The first malleable material provides the central region of the lower surface with a first stiffness and the second malleable material provides the peripheral region of the lower surface with a second stiffness that is different than the first stiffness.Type: GrantFiled: March 3, 2022Date of Patent: December 26, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Ping Chen, Ren-Dou Lee, Sheng-Tai Peng, Tsung-Lung Lai, Tzi-Yi Shieh, Chien-Wei Chang
-
Publication number: 20230256561Abstract: The present disclosure provides a method of chemical mechanical polish operation and a chemical mechanical polish operation system. The method includes obtaining a first input parameter and a second input parameter, wherein the first input parameter is associated with an additive of a slurry, and the second input parameter is associated with a characteristic of a process apparatus, determining an output parameter associated with the process apparatus based on the first input parameter and the second input parameter, securing a workpiece by a head over a platen in the process apparatus, supplying the slurry with the additive over the platen with the additive configured with the first parameter, and polishing a surface of the workpiece by operating the process apparatus configured with the output parameter.Type: ApplicationFiled: February 17, 2022Publication date: August 17, 2023Inventors: CHUNHUNG CHEN, YU-CHU HSU, REN-DOU LEE
-
Patent number: 11688620Abstract: In an embodiment, a system includes: a cassette comprising a slit opening configured to house a wafer; a blade configured to move the wafer to and from the slit opening by extending into the slit opening, wherein a blade thickness of the blade is at most ? of a height of the slit opening and wherein the blade is configured to secure the wafer within a pocket on the blade that is at least ? of a wafer thickness of the wafer.Type: GrantFiled: June 22, 2022Date of Patent: June 27, 2023Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Chih Chen, Yao-Min Yu, Ching-Ling Lee, Ren-Dou Lee
-
Publication number: 20220392796Abstract: In an embodiment, a system includes: a cassette comprising a slit opening configured to house a wafer; a blade configured to move the wafer to and from the slit opening by extending into the slit opening, wherein a blade thickness of the blade is at most ? of a height of the slit opening and wherein the blade is configured to secure the wafer within a pocket on the blade that is at least ? of a wafer thickness of the wafer.Type: ApplicationFiled: June 22, 2022Publication date: December 8, 2022Inventors: Chien-Chih CHEN, Yao-Min YU, Ching-Ling LEE, Ren-Dou LEE
-
Patent number: 11380569Abstract: In an embodiment, a system includes: a cassette comprising a slit opening configured to house a wafer; a blade configured to move the wafer to and from the slit opening by extending into the slit opening, wherein a blade thickness of the blade is at most ? of a height of the slit opening and wherein the blade is configured to secure the wafer within a pocket on the blade that is at least ? of a wafer thickness of the wafer.Type: GrantFiled: June 22, 2020Date of Patent: July 5, 2022Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Chih Chen, Yao-Min Yu, Ching-Ling Lee, Ren-Dou Lee
-
Publication number: 20220184773Abstract: In some embodiments, the present disclosure relates to a chemical mechanical planarization (CMP) tool. The CMP tool includes a carrier and a malleable membrane coupled to the carrier and having a lower surface facing away from the carrier. The lower surface of the malleable membrane includes a first malleable material within a central region of the lower surface and a second malleable material within a peripheral region of the lower surface, which surrounds the central region. The first malleable material provides the central region of the lower surface with a first stiffness and the second malleable material provides the peripheral region of the lower surface with a second stiffness that is different than the first stiffness.Type: ApplicationFiled: March 3, 2022Publication date: June 16, 2022Inventors: Cheng-Ping Chen, Ren-Dou Lee, Sheng-Tai Peng, Tsung-Lung Lai, Tzi-Yi Shieh, Chien-Wei Chang
-
Patent number: 11267099Abstract: In some embodiments, the present disclosure, in some embodiments, relates to a method of forming a CMP membrane. The method is performed by providing a malleable material within a cavity within a membrane mold. The cavity has a central region and a peripheral region surrounding the central region. The malleable material within the cavity is cured to form a membrane. Curing the malleable material is performed by heating the malleable material within the central region of the membrane mold to a first temperature and heating the malleable material within the peripheral region of the membrane mold to a second temperature that is greater than the first temperature.Type: GrantFiled: May 31, 2018Date of Patent: March 8, 2022Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Cheng-Ping Chen, Ren-Dou Lee, Sheng-Tai Peng, Tsung-Lung Lai, Tzi-Yi Shieh, Chien-Wei Chang
-
Patent number: 11192778Abstract: A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.Type: GrantFiled: July 13, 2020Date of Patent: December 7, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Jui Chen, I-Shi Wang, Ren-Dou Lee, Jen-Hao Liu
-
Patent number: 11034578Abstract: A multi-layer sealing film for high seal yield is provided. In some embodiments, a substrate comprises a vent opening extending through the substrate, from an upper side of the substrate to a lower side of the substrate. The upper side of the substrate has a first pressure, and the lower side of the substrate has a second pressure different than the first pressure. The multi-layer sealing film covers and seals the vent opening to prevent the first pressure from equalizing with the second pressure through the vent opening. Further, the multi-layer sealing film comprises a pair of metal layers and a barrier layer sandwiched between metal layers. Also provided is a microelectromechanical systems (MEMS) package comprising the multilayer sealing film, and a method for manufacturing the multi-layer sealing film.Type: GrantFiled: May 13, 2020Date of Patent: June 15, 2021Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chien Yang, Ming-Lun Shih, Ren-Dou Lee, Jen-Hao Liu
-
Publication number: 20200388520Abstract: In an embodiment, a system includes: a cassette comprising a slit opening configured to house a wafer; a blade configured to move the wafer to and from the slit opening by extending into the slit opening, wherein a blade thickness of the blade is at most ? of a height of the slit opening and wherein the blade is configured to secure the wafer within a pocket on the blade that is at least ? of a wafer thickness of the wafer.Type: ApplicationFiled: June 22, 2020Publication date: December 10, 2020Inventors: Chien-Chih Chen, Yao-Min Yu, Ching-Ling Lee, Ren-Dou Lee
-
Publication number: 20200339413Abstract: A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.Type: ApplicationFiled: July 13, 2020Publication date: October 29, 2020Inventors: Yu-Jui CHEN, I-Shi WANG, Ren-Dou LEE, Jen-Hao LIU
-
Patent number: 10759654Abstract: The present disclosure relates to a method for manufacturing a microelectromechanical systems (MEMS) package. The method comprises providing a CMOS IC including CMOS devices arranged within a CMOS substrate. The method further comprises forming and patterning a metal layer over the CMOS substrate to form an anti-stiction layer and a fixed electrode plate and forming a rough top surface for the anti-stiction layer. The method further comprises providing a MEMS IC comprising a moveable mass arranged within a recess of a MEMS substrate and bonding the CMOS IC to the MEMS IC to enclose a cavity between the moveable mass and the fixed electrode plate and the anti-stiction layer.Type: GrantFiled: December 21, 2018Date of Patent: September 1, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Jui Chen, I-Shi Wang, Ren-Dou Lee, Jen-Hao Liu
-
Publication number: 20200270121Abstract: A multi-layer sealing film for high seal yield is provided. In some embodiments, a substrate comprises a vent opening extending through the substrate, from an upper side of the substrate to a lower side of the substrate. The upper side of the substrate has a first pressure, and the lower side of the substrate has a second pressure different than the first pressure. The multi-layer sealing film covers and seals the vent opening to prevent the first pressure from equalizing with the second pressure through the vent opening. Further, the multi-layer sealing film comprises a pair of metal layers and a barrier layer sandwiched between metal layers. Also provided is a microelectromechanical systems (MEMS) package comprising the multilayer sealing film, and a method for manufacturing the multi-layer sealing film.Type: ApplicationFiled: May 13, 2020Publication date: August 27, 2020Inventors: Chih-Chien Yang, Ming-Lun Shih, Ren-Dou Lee, Jen-Hao Liu
-
Patent number: 10710872Abstract: A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.Type: GrantFiled: December 6, 2017Date of Patent: July 14, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Jui Chen, I-Shi Wang, Ren-Dou Lee, Jen-Hao Liu
-
Patent number: 10699931Abstract: In an embodiment, a system includes: a cassette comprising a slit opening configured to house a wafer; a blade configured to move the wafer to and from the slit opening by extending into the slit opening, wherein a blade thickness of the blade is at most ? of a height of the slit opening and wherein the blade is configured to secure the wafer within a pocket on the blade that is at least ? of a wafer thickness of the wafer.Type: GrantFiled: September 6, 2018Date of Patent: June 30, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chien-Chih Chen, Yao-Min Yu, Ching-Ling Lee, Ren-Dou Lee
-
Patent number: 10676343Abstract: A multi-layer sealing film for high seal yield is provided. In some embodiments, a substrate comprises a vent opening extending through the substrate, from an upper side of the substrate to a lower side of the substrate. The upper side of the substrate has a first pressure, and the lower side of the substrate has a second pressure different than the first pressure. The multi-layer sealing film covers and seals the vent opening to prevent the first pressure from equalizing with the second pressure through the vent opening. Further, the multi-layer sealing film comprises a pair of metal layers and a barrier layer sandwiched between metal layers. Also provided is a microelectromechanical systems (MEMS) package comprising the multilayer sealing film, and a method for manufacturing the multi-layer sealing film.Type: GrantFiled: November 28, 2018Date of Patent: June 9, 2020Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chien Yang, Ming-Lun Shih, Ren-Dou Lee, Jen-Hao Liu
-
Publication number: 20200172393Abstract: Methods for improving wafer bonding performance are disclosed herein. In some embodiments, a method for bonding a pair of semiconductor substrates is disclosed. The method includes: processing at least one of the pair of semiconductor substrates, and bonding the pair of semiconductor substrates together. Each of the pair of semiconductor substrates is processed by: performing at least one chemical vapor deposition (CVD), and performing at least one chemical mechanical polishing (CMP). One of the at least one CVD is performed after all CMP performed before bonding.Type: ApplicationFiled: November 26, 2019Publication date: June 4, 2020Inventors: Chien-Wei CHANG, Ya-Jen SHEUH, Ren-Dou LEE, Yi-Chih CHANG, Yi-Hsun CHIU, Yuan-Hsin CHI
-
Publication number: 20200164482Abstract: Described herein are multi-layered windows for use in chemical-mechanical planarization (CMP) systems and CMP processes. The multi-layered windows of the present disclosure include a transparent structural layer and a hydrophilic surfactant applied to at least a portion of at least one surface of the transparent structural layer. Such multi-layered windows may be in the polishing pad, the platen, or both.Type: ApplicationFiled: September 3, 2019Publication date: May 28, 2020Inventors: Shih-Chung Chen, Yi-Shao Lin, Sheng-Tai Peng, Ya-Jen Sheuh, Hung-Lin Chen, Ren-Dou Lee
-
Patent number: 10322928Abstract: A multi-layer sealing film for high seal yield is provided. In some embodiments, a substrate comprises a vent opening extending through the substrate, from an upper side of the substrate to a lower side of the substrate. The upper side of the substrate has a first pressure, and the lower side of the substrate has a second pressure different than the first pressure. The multi-layer sealing film covers and seals the vent opening to prevent the first pressure from equalizing with the second pressure through the vent opening. Further, the multi-layer sealing film comprises a pair of metal layers and a barrier layer sandwiched between metal layers. Also provided is a microelectromechanical systems (MEMS) package comprising the multilayer sealing film, and a method for manufacturing the multi-layer sealing film.Type: GrantFiled: September 1, 2017Date of Patent: June 18, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chih-Chien Yang, Ming-Lun Shih, Ren-Dou Lee, Jen-Hao Liu