Patents by Inventor Ren-Dou Lee
Ren-Dou Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10319557Abstract: Ion generators for ion implanters are provided. The ion generator for an ion implanter includes an ion source arc chamber including an arc chamber housing and a thermal electron emitter coupled to the arc chamber housing. In addition, the thermal electron emitter includes a filament and a cathode, and the cathode has a solid top portion made of a work function modified conductive material including tungsten (W) and a work function modification metal.Type: GrantFiled: August 31, 2017Date of Patent: June 11, 2019Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Tai-Kun Kao, Tsung-Min Lin, Jen-Chung Chiu, Ren-Dou Lee
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Publication number: 20190119099Abstract: The present disclosure relates to a method for manufacturing a microelectromechanical systems (MEMS) package. The method comprises providing a CMOS IC including CMOS devices arranged within a CMOS substrate. The method further comprises forming and patterning a metal layer over the CMOS substrate to form an anti-stiction layer and a fixed electrode plate and forming a rough top surface for the anti-stiction layer. The method further comprises providing a MEMS IC comprising a moveable mass arranged within a recess of a MEMS substrate and bonding the CMOS IC to the MEMS IC to enclose a cavity between the moveable mass and the fixed electrode plate and the anti-stiction layer.Type: ApplicationFiled: December 21, 2018Publication date: April 25, 2019Inventors: Yu-Jui Chen, I-Shi Wang, Ren-Dou Lee, Jen-Hao Liu
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Publication number: 20190091829Abstract: In some embodiments, the present disclosure, in some embodiments, relates to a method of forming a CMP membrane. The method is performed by providing a malleable material within a cavity within a membrane mold. The cavity has a central region and a peripheral region surrounding the central region. The malleable material within the cavity is cured to form a membrane. Curing the malleable material is performed by heating the malleable material within the central region of the membrane mold to a first temperature and heating the malleable material within the peripheral region of the membrane mold to a second temperature that is greater than the first temperature.Type: ApplicationFiled: May 31, 2018Publication date: March 28, 2019Inventors: Cheng-Ping Chen, Ren-Dou Lee, Sheng-Tai Peng, Tsung-Lung Lai, Tzi-Yi Shieh, Chien-Wei Chang
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Publication number: 20190092622Abstract: A multi-layer sealing film for high seal yield is provided. In some embodiments, a substrate comprises a vent opening extending through the substrate, from an upper side of the substrate to a lower side of the substrate. The upper side of the substrate has a first pressure, and the lower side of the substrate has a second pressure different than the first pressure. The multi-layer sealing film covers and seals the vent opening to prevent the first pressure from equalizing with the second pressure through the vent opening. Further, the multi-layer sealing film comprises a pair of metal layers and a barrier layer sandwiched between metal layers. Also provided is a microelectromechanical systems (MEMS) package comprising the multilayer sealing film, and a method for manufacturing the multi-layer sealing film.Type: ApplicationFiled: November 28, 2018Publication date: March 28, 2019Inventors: Chih-Chien Yang, Ming-Lun Shih, Ren-Dou Lee, Jen-Hao Liu
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Publication number: 20190074205Abstract: In an embodiment, a system includes: a cassette comprising a slit opening configured to house a wafer; a blade configured to move the wafer to and from the slit opening by extending into the slit opening, wherein a blade thickness of the blade is at most ? of a height of the slit opening and wherein the blade is configured to secure the wafer within a pocket on the blade that is at least ? of a wafer thickness of the wafer.Type: ApplicationFiled: September 6, 2018Publication date: March 7, 2019Inventors: Chien-Chih CHEN, Yao-Min Yu, Ching-Ling Lee, Ren-Dou Lee
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Publication number: 20190066967Abstract: Ion generators for ion implanters are provided. The ion generator for an ion implanter includes an ion source arc chamber including an arc chamber housing and a thermal electron emitter coupled to the arc chamber housing. In addition, the thermal electron emitter includes a filament and a cathode, and the cathode has a solid top portion made of a work function modified conductive material including tungsten (W) and a work function modification metal.Type: ApplicationFiled: August 31, 2017Publication date: February 28, 2019Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tai-Kun KAO, Tsung-Min LIN, Jen-Chung CHIU, Ren-Dou LEE
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Patent number: 10173886Abstract: The present disclosure relates to a MEMS package with a rough metal anti-stiction layer, to improve stiction characteristics, and an associated method of formation. In some embodiments, the MEMS package includes a MEMS IC bonded to a CMOS IC. The CMOS IC has a CMOS substrate and an interconnect structure disposed over the CMOS substrate. The interconnect structure includes a plurality of metal layers disposed within a plurality of dielectric layers. The MEMS IC is bonded to the CMOS IC, enclosing a cavity between the MEMS IC and the CMOS IC and a moveable mass arranged in the cavity. The MEMS package further includes an anti-stiction layer disposed under the moveable mass. The anti-stiction layer is made of metal and has a rough top surface.Type: GrantFiled: January 31, 2018Date of Patent: January 8, 2019Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Jui Chen, I-Shi Wang, Ren-Dou Lee, Jen-Hao Liu
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Publication number: 20180179047Abstract: The present disclosure relates to a MEMS package with a rough metal anti-stiction layer, to improve stiction characteristics, and an associated method of formation. In some embodiments, the MEMS package includes a MEMS IC bonded to a CMOS IC. The CMOS IC has a CMOS substrate and an interconnect structure disposed over the CMOS substrate. The interconnect structure includes a plurality of metal layers disposed within a plurality of dielectric layers. The MEMS IC is bonded to the CMOS IC, enclosing a cavity between the MEMS IC and the CMOS IC and a moveable mass arranged in the cavity. The MEMS package further includes an anti-stiction layer disposed under the moveable mass. The anti-stiction layer is made of metal and has a rough top surface.Type: ApplicationFiled: January 31, 2018Publication date: June 28, 2018Inventors: Yu-Jui Chen, I-Shi Wang, Ren-Dou Lee, Jen-Hao Liu
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Publication number: 20180162720Abstract: A method includes: providing a first substrate on which a plurality of first semiconductor devices is formed; providing a second substrate on which a plurality of second semiconductor devices is formed; and coupling the first and second substrates by contacting respective dummy pads of the first and second substrates, wherein at least one of the dummy pads of the first and second substrates comprises plural peaks and valleys.Type: ApplicationFiled: December 6, 2017Publication date: June 14, 2018Inventors: Yu-Jui Cheng, I-Shi Wang, Ren-Dou Lee, Jen-Hao Liu
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Publication number: 20180148320Abstract: A multi-layer sealing film for high seal yield is provided. In some embodiments, a substrate comprises a vent opening extending through the substrate, from an upper side of the substrate to a lower side of the substrate. The upper side of the substrate has a first pressure, and the lower side of the substrate has a second pressure different than the first pressure. The multi-layer sealing film covers and seals the vent opening to prevent the first pressure from equalizing with the second pressure through the vent opening. Further, the multi-layer sealing film comprises a pair of metal layers and a barrier layer sandwiched between metal layers. Also provided is a microelectromechanical systems (MEMS) package comprising the multilayer sealing film, and a method for manufacturing the multi-layer sealing film.Type: ApplicationFiled: September 1, 2017Publication date: May 31, 2018Inventors: Chih-Chien Yang, Ming-Lun Shih, Ren-Dou Lee, Jen-Hao Liu
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Patent number: 9884755Abstract: The present disclosure relates to a MEMS package with a rough metal anti-stiction layer, to improve stiction characteristics, and an associated method of formation. In some embodiments, the MEMS package includes a MEMS IC bonded to a CMOS IC. The CMOS IC has a CMOS substrate and an interconnect structure disposed over the CMOS substrate. The interconnect structure includes a plurality of metal layers disposed within a plurality of dielectric layers. The MEMS IC is bonded to an upper surface of the interconnect structure and, in cooperation with the CMOS IC, enclosing a cavity between the MEMS IC and the CMOS IC. The MEMS IC has a moveable mass arranged in the cavity. The MEMS package further includes an anti-stiction layer disposed on the upper surface of the interconnect structure under the moveable mass. The anti-stiction layer is made of metal and has a rough top surface.Type: GrantFiled: January 26, 2016Date of Patent: February 6, 2018Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Yu-Jui Chen, I-Shi Wang, Ren-Dou Lee, Jen-Hao Liu
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Publication number: 20170210612Abstract: The present disclosure relates to a MEMS package with a rough metal anti-stiction layer, to improve stiction characteristics, and an associated method of formation. In some embodiments, the MEMS package includes a MEMS IC bonded to a CMOS IC. The CMOS IC has a CMOS substrate and an interconnect structure disposed over the CMOS substrate. The interconnect structure includes a plurality of metal layers disposed within a plurality of dielectric layers. The MEMS IC is bonded to an upper surface of the interconnect structure and, in cooperation with the CMOS IC, enclosing a cavity between the MEMS IC and the CMOS IC. The MEMS IC has a moveable mass arranged in the cavity. The MEMS package further includes an anti-stiction layer disposed on the upper surface of the interconnect structure under the moveable mass. The anti-stiction layer is made of metal and has a rough top surface.Type: ApplicationFiled: January 26, 2016Publication date: July 27, 2017Inventors: Yu-Jui Chen, I-Shi Wang, Ren-Dou Lee, Jen-Hao Liu
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Patent number: 9481567Abstract: A micro electro mechanical system (MEMS) structure is provided, which includes a first substrate, a second substrate, a MEMS device and a hydrophobic semiconductor layer. The first substrate has a first portion. The second substrate is substantially parallel to the first substrate and has a second portion substantially aligned with the first portion. The MEMS device is between the first portion and the second portion. The hydrophobic semiconductor layer is made of germanium (Ge), silicon (Si) or a combination thereof on the first portion, the second portion or the first portion and the second portion and faces toward the MEMS device. A cap substrate for a MEMS device and a method of fabricating the same are also provided.Type: GrantFiled: June 12, 2014Date of Patent: November 1, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: I-Shi Wang, Yu-Jui Chen, Ting-Ying Chien, Jen-Hao Liu, Ren-Dou Lee
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Publication number: 20160005694Abstract: A semiconductor package structure includes a first wafer and a second wafer. The first wafer has a concave portion. The concave portion has a bottom surface and at least one sidewall adjacent to the bottom surface. An obtuse angle is formed between the bottom surface and the sidewall. The second wafer is disposed on the first wafer and has a protruding portion. When the protruding portion enters an opening of the concave portion, the protruding portion slides along the sidewall to the bottom surface, such that the protruding portion is coupled to the concave portion.Type: ApplicationFiled: July 2, 2014Publication date: January 7, 2016Inventors: Ting-Ying CHIEN, I-Shi WANG, Jen-Hao LIU, Ren-Dou LEE
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Patent number: 9230918Abstract: A semiconductor package structure includes a first wafer and a second wafer. The first wafer has a concave portion. The concave portion has a bottom surface and at least one sidewall adjacent to the bottom surface. An obtuse angle is formed between the bottom surface and the sidewall. The second wafer is disposed on the first wafer and has a protruding portion. When the protruding portion enters an opening of the concave portion, the protruding portion slides along the sidewall to the bottom surface, such that the protruding portion is coupled to the concave portion.Type: GrantFiled: July 2, 2014Date of Patent: January 5, 2016Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Ting-Ying Chien, I-Shi Wang, Jen-Hao Liu, Ren-Dou Lee
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Publication number: 20150360938Abstract: A micro electro mechanical system (MEMS) structure is provided, which includes a first substrate, a second substrate, a MEMS device and a hydrophobic semiconductor layer. The first substrate has a first portion. The second substrate is substantially parallel to the first substrate and has a second portion substantially aligned with the first portion. The MEMS device is between the first portion and the second portion. The hydrophobic semiconductor layer is made of germanium (Ge), silicon (Si) or a combination thereof on the first portion, the second portion or the first portion and the second portion and faces toward the MEMS device. A cap substrate for a MEMS device and a method of fabricating the same are also provided.Type: ApplicationFiled: June 12, 2014Publication date: December 17, 2015Inventors: I-Shi Wang, Yu-Jui Chen, Ting-Ying Chien, Jen-Hao Liu, Ren-Dou Lee
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Patent number: 9127356Abstract: A sputtering target is provided that includes a planar backing plate and a target material formed over the planar backing plate and including an uneven sputtering surface including thick portions and thin portions and configured in conjunction with a sputtering apparatus such as a magnetron sputtering tool with a fixed magnet arrangement. The uneven surface is designed in conjunction with the magnetic fields that will be produced by the magnet arrangement such that the thicker target portions are positioned at locations where target erosion occurs at a high rate. Also provided is the magnetron sputtering system and a method for utilizing the target with uneven sputtering surface such that the thickness across the target to become more uniform in time as the target is used.Type: GrantFiled: August 18, 2011Date of Patent: September 8, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chia-Liang Chueh, Kuo-Chou Chen, Ren-Dou Lee, Hsien-Liang Meng, Chun-Wei Lin
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Publication number: 20130043120Abstract: A sputtering target is provided that includes a planar backing plate and a target material formed over the planar backing plate and including an uneven sputtering surface including thick portions and thin portions and configured in conjunction with a sputtering apparatus such as a magnetron sputtering tool with a fixed magnet arrangement. The uneven surface is designed in conjunction with the magnetic fields that will be produced by the magnet arrangement such that the thicker target portions are positioned at locations where target erosion occurs at a high rate. Also provided is the magnetron sputtering system and a method for utilizing the target with uneven sputtering surface such that the thickness across the target to become more uniform in time as the target is used.Type: ApplicationFiled: August 18, 2011Publication date: February 21, 2013Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Liang CHUEH, Kuo-Chou CHEN, Ren-Dou LEE, Hsien-Liang MENG, Chun-Wei LIN
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Patent number: 6531415Abstract: A method for forming upon a substrate employed within a microelectronics fabrication a silicon nitride dielectric layer with attenuated defects and inhomogeneities. There is provided one or more substrates. There is then provided a reactor tube which is part of an apparatus suitable for providing various gases at elevated temperatures. There is then purged the reactor tube with an inert gas in a low temperature cycle purge (LTCP) step at a temperature below deposition temperature. There is then placed the substrate(s) within a reactor tube. There is then deposited a silicon nitride dielectric layer upon the substrate(s), employing silane and ammonia gases employing a low pressure chemical vapor deposition (LPCVD) method. There is then purged the reaction tube at a temperature below the deposition temperature, followed by removal of the substrate carrier with attenuated formation of particulates and inhomogeneities within and about the silicon nitride layer and reaction tube.Type: GrantFiled: January 30, 2002Date of Patent: March 11, 2003Assignee: Taiwan Semiconductor Manufacturing CompanyInventors: Wan-Cheng Yang, Ren-Dou Lee