Abstract: A memory device is disclosed, including a memory array and a selection circuit. At least one first faulty cell and at least one second faulty cell that are in the memory array store data corresponding to, respectively, first and second fields of a floating-point number. The selection circuit identifies the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell. The selection circuit further outputs a fault address of the at least one first faulty cell to a redundancy analyzer circuit for replacing the at least one first faulty cell.

Abstract: A neural network is provided to include a layer that has a weight set. The neural network is trained based on a first compression quality level, where the weight set and a first set of batch normalization coefficients are used in said layer, so the weight set and the first set of batch normalization coefficients are trained with respect to the first compression quality level. Then, the neural network is trained based on a second compression quality level, where the weight set that has been trained with respect to the first compression quality level and a second set of batch normalization coefficients are used in said layer, so the weight set is trained with respect to both of the first and second compression quality levels, and the second set of batch normalization coefficients is trained with respect to the second compression quality level.

Abstract: A floating-point number operation method applied to multiplication operation of a first floating-point number and a second floating-point number is provided. The first floating point number includes a first symbol, a first exponent and a first mantissa. The second floating point number includes a second symbol, a second exponent and a second mantissa. The method includes using an arithmetic unit to perform: comparing the first exponent to an exponent threshold, wherein when the first exponent is not less than the exponent threshold, generating a mantissa operation result by multiplying the first mantissa and the second mantissa when the first exponent is not less than the exponent threshold value; and generating a calculated floating point number according to the mantissa operation result and an exponent operation result of the first exponent and the second exponent.

Abstract: A bit-serial computing device includes a computing circuit and a scaler. The computing circuit includes multiple MAC slices, and receives a multiplier vector and a multiplicand vector that contains multiple multiplicand inputs. Each multiplicand input contains multiple multiplicand segments that have different significances. The significances respectively correspond to the MAC slices. Correspondence between the significances and the MAC slices is variable. Each MAC slice calculates an inner product of the multiplier vector and a vector that is constituted by the multiplicand segments of the multiplicand inputs having the significance corresponding to the MAC slice. With respect to each MAC slice, the scaler multiplies the inner product that is calculated by the MAC slice by a weighting ratio that represents the significance corresponding to the MAC slice, so as to obtain a scaled inner product that corresponds to the MAC slice.

Abstract: A method for facilitating recovery from a crash of a solid-state storage device (SSD) is adapted to be implemented by an SSD controller of the SSD that receives a write request. The method includes: assigning a write request identifier (WID) and a request size in a spare area of each written page of the SSD; counting a number of appearances of the WID in all written page(s) to result in a WID count; determining whether the WID count is equal to the request size; and determining that the write request is completed and is eligible for recovery after a crash of the SSD when it is determined that the WID count is equal to the request size.

Abstract: A memory device is disclosed, including a memory array and a selection circuit. At least one first faulty cell and at least one second faulty cell that are in the memory array store data corresponding to, respectively, first and second fields of a floating-point number. The selection circuit identifies the at least one first faulty cell and the at least one second faulty cell based on a priority of a cell replacement operation which indicates that a priority of the at least one first faulty cell is higher than that of the at least one second faulty cell. The selection circuit further outputs a fault address of the at least one first faulty cell to a redundancy analyzer circuit for replacing the at least one first faulty cell.

Abstract: A method for facilitating recovery from a crash of a solid-state storage device (SSD) is adapted to be implemented by an SSD controller of the SSD that receives a write request. The method includes: assigning a write request identifier (WID) and a request size in a spare area of each written page of the SSD; counting a number of appearances of the WID in all written page(s) to result in a WID count; determining whether the WID count is equal to the request size; and determining that the write request is completed and is eligible for recovery after a crash of the SSD when it is determined that the WID count is equal to the request size.

Abstract: A memory chip capable of performing artificial intelligence operation and an operation method thereof are provided. The memory chip includes a memory array and an artificial intelligence engine. The memory array is configured to store input feature data and a plurality of weight data. The input feature data includes a plurality of first subsets, and each of the weight data includes a plurality of second subsets. The artificial intelligence engine includes a plurality of feature detectors. The artificial intelligence engine is configured to access the memory array to obtain the input feature data and the weight data. Each of the feature detectors selects at least one of the second subsets from the corresponding weight data as a selected subset based on a weight index, and the feature detectors perform a neural network operation based on the selected subsets and the corresponding first subsets.

Abstract: A processor adapted for neural network operation is provided to include a scratchpad memory, a processor core, a neural network accelerator coupled to the processor core, and a arbitration unit coupled to the scratchpad memory, the processor core and the neural network accelerator. The processor core and the neural network accelerator share the scratchpad memory via the arbitration unit.

Abstract: A memory chip capable of performing artificial intelligence operation and an operation method thereof are provided. The memory chip includes a memory array and an artificial intelligence engine. The memory array is configured to store input feature data and a plurality of weight data. The input feature data includes a plurality of first subsets, and each of the weight data includes a plurality of second subsets. The artificial intelligence engine includes a plurality of feature detectors. The artificial intelligence engine is configured to access the memory array to obtain the input feature data and the weight data. Each of the feature detectors selects at least one of the second subsets from the corresponding weight data as a selected subset based on a weight index, and the feature detectors perform a neural network operation based on the selected subsets and the corresponding first subsets.

Abstract: A method for facilitating recovery from a crash of a solid-state storage device (SSD) is adapted to be implemented by an SSD controller of the SSD that receives a write request. The method includes: assigning a write request identifier (WID) and a request size in a spare area of each written page of the SSD; counting a number of appearances of the WID in all written page(s) to result in a WID count; determining whether the WID count is equal to the request size; and determining that the write request is completed and is eligible for recovery after a crash of the SSD when it is determined that the WID count is equal to the request size.

Abstract: A method of training an N-bit neural network (N?2), is proposed to include: providing the N-bit neural network that includes a plurality of weights to be trained, each of the weights being composed of N bits that respectively correspond to N bit orders which are divided into multiple bit order groups, wherein the bits of the weights are divided, based on the bit orders to which the bits of the weights correspond, into multiple bit groups that respectively correspond to the bit order groups; and determining the weights for the N-bit neural network by training the bit groups one by one.

Abstract: A method for testing firmware of an SSD includes: controlling a main memory to emulate volatile and non-volatile memories of the SSD, fetching a testing sequence and a testing criterion, fetching read/write operations from binary codes generated by compiling the firmware, determining whether the read/write operations are associated with a marker, executing the read/write operations when a result of determination is affirmative, otherwise discarding a read/write of data, monitoring whether processes of executing of the read/write operations meet the testing criterion, and generating a result of a test of the firmware when it is monitored that the testing criterion is met.

Abstract: A method for testing firmware of an SSD includes: controlling a main memory to emulate volatile and non-volatile memories of the SSD, fetching a testing sequence and a testing criterion, fetching read/write operations from binary codes generated by compiling the firmware, determining whether the read/write operations are associated with a marker, executing the read/write operations when a result of determination is affirmative, otherwise discarding a read/write of data, monitoring whether processes of executing of the read/write operations meet the testing criterion, and generating a result of a test of the firmware when it is monitored that the testing criterion is met.

Abstract: A memory system includes a memory device, a channel and a memory controller device. The memory device includes: a memory array having a read latency, and a write latency that is longer than the read latency; a buffer for two-way data transfer with the memory array; and a transceiver for two-way data transfer with the buffer. The memory controller device is for two-way data transfer with the transceiver through the channel. The memory controller device transmits write data at a write bandwidth for receipt by the transceiver. The transceiver transmits read data at a read bandwidth that is greater than the write bandwidth for receipt by the memory controller device.

Abstract: In a caching method implemented by a data storage system, a data word as user data is encoded into a codeword that is then written into an area of a cache memory. The codeword includes a data portion, a checksum parity portion and an error correction code (ECC) parity portion. In response to a read request for the user data, the codeword read from the cache memory is decoded based on the ECC parity portion to correct one or more bit errors within the data portion so as to generate a read data portion and a read checksum parity portion. Upon identifying that a validating checksum portion generated based on the read data portion matches the read checksum parity portion, the read data portion serving as the user data is outputted. Otherwise, a data storage unit outputs the user data previously stored therein.

Abstract: An operating method of a storage device is provided. The operating method comprises the following steps. First, a first data is read from a target address of a first storage unit. Then, an assisting unit checks whether the target address is corresponding to a second data stored in a second storage unit. If the target address is corresponding to the second data, the assisting unit updates the first data according to the second data to generate an updated data. Next, an Error Correction Code (ECC) performs a decoding process on the updated data to generate a decoded data.

Abstract: The present disclosure relates, according to some embodiments, to a data writing method in a storage system. The method comprises receiving data by the storage media controller, reading a non-volatile memory operation mode in the memory unit by a central control unit, in which the mode corresponds to a data reliability lower than the data reliability requirement of the storage system, reading a data reliability reduction condition in the memory unit by the central control unit, determining whether a system information related to the data meets the condition by the central control unit, and controlling the media control unit to write the data into the non-volatile memory according to the mode by the central control unit when the system information meets the condition.

Abstract: A method for operating a memory includes receiving a command to program a data value at a memory cell, and an indication of which write mode in a plurality of write modes to use. Write modes in the plurality are characterized by different sets of resistance ranges that correspond to data values stored in the memory cell. The method includes executing a program operation according to the indicated one in the plurality of write modes to program the data value in the memory cell. The plurality of write modes includes a first write mode and a second write mode corresponding to shorter data retention than the first write mode. The first and second write modes are characterized by first and second sets of resistance ranges in the different sets of resistance ranges. The method includes periodically refreshing data values in memory cells storing data in the second write mode.

Abstract: In a caching method implemented by a data storage system, a data word as user data is encoded into a codeword that is then written into an area of a cache memory. The codeword includes a data portion, a checksum parity portion and an error correction code (ECC) parity portion. In response to a read request for the user data, the codeword read from the cache memory is decoded based on the ECC parity portion to correct one or more bit errors within the data portion so as to generate a read data portion and a read checksum parity portion. Upon identifying that a validating checksum portion generated based on the read data portion matches the read checksum parity portion, the read data portion serving as the user data is outputted. Otherwise, a data storage unit outputs the user data previously stored therein.