Abstract: An operating method of a storage device is provided. The operating method comprises the following steps. First, a first data is read from a target address of a first storage unit. Then, an assisting unit checks whether the target address is corresponding to a second data stored in a second storage unit. If the target address is corresponding to the second data, the assisting unit updates the first data according to the second data to generate an updated data. Next, an Error Correction Code (ECC) performs a decoding process on the updated data to generate a decoded data.

Abstract: A method for operating a memory includes receiving a command to program a data value at a memory cell, and an indication of which write mode in a plurality of write modes to use. Write modes in the plurality are characterized by different sets of resistance ranges that correspond to data values stored in the memory cell. The method includes executing a program operation according to the indicated one in the plurality of write modes to program the data value in the memory cell. The plurality of write modes includes a first write mode and a second write mode corresponding to shorter data retention than the first write mode. The first and second write modes are characterized by first and second sets of resistance ranges in the different sets of resistance ranges. The method includes periodically refreshing data values in memory cells storing data in the second write mode.

Abstract: An exemplary embodiment of a circuit board is provided. The circuit board is compatible to a first chip with a first pin number, and a second chip with a second pin number, comprising a plurality of first pads, second pads and third pads. The arrangements of the first and second pads are fit to the pin arrangement of the first chip, and the arrangements of the first and third pads are fit to the pin arrangement of the second chip. The first chip can be placed on the circuit board via the first and second pads, and the second chip can be placed on the circuit board via the first and third pads.

Abstract: A digital video multiplex processing method comprises the following steps: setting a normal play index and a fast play index; performing a normal recording/playback action of a video data; determining whether to let the video data enter a cue-and-jump action; taking track of the fast play index in the video data; performing conversion of the video data; and setting the normal play index to be equal to the fast play index. A digital video multiplex processing device comprises a video medium readout unit, a drive interface unit, a data regulation unit, a data buffer unit, an image decoding unit, a sound decoding unit, an image processing unit, a sound processing unit, and a control unit. The control unit is used to receive operation instructions of a user to control the operation of the digital video multiplex processing device.

Abstract: A digital video multiplex processing method comprises the following steps: setting a normal play index and a fast play index; performing a normal recording/playback action of a video data; determining whether to let the video data enter a cue-and-jump action; taking track of the fast play index in the video data; performing conversion of the video data; and setting the normal play index to be equal to the fast play index. A digital video multiplex processing device comprises a video medium readout unit, a drive interface unit, a data regulation unit, a data buffer unit, an image decoding unit, a sound decoding unit, an image processing unit, a sound processing unit, and a control unit. The control unit is used to receive operation instructions of a user to control the operation of the digital video multiplex processing device.