Patents by Inventor Rene Glaise
Rene Glaise has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8995445Abstract: In a network device packets are marked with sequence identifiers at ingress of the device, switched through a plurality of switching planes and re-sequenced on a per flow basis at egress of the device. The re-sequencing system includes a controller that allocates to each received data packet a temporary storage location in a packet buffer. A plurality of output registers are provided, with each one associated with a flow. A pointer uses predefined parameters to point to an output register that has been previously assigned to receive data packets from the corresponding flow. Parameters in the pointed output register are correlated with parameters in a received packet to determine if the received packet is next in sequence to packets processed through a particular queue.Type: GrantFiled: November 26, 2003Date of Patent: March 31, 2015Assignee: International Business Machines CorporationInventors: Francois Le Maut, Rene Glaise, Michel Poret, Rene Gallezot
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Patent number: 8085789Abstract: A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism is disclosed. An egress location for an ingress port is selected based on degrees of freedom for the selection mechanism. The degree of freedom can be derived from the collapsed virtual output queuing array by determining a number of egress locations to which an ingress port may send packets and determining a number of ingress ports from which an egress location can receive packets. Analyzing all the queued packets for assignment to an egress location, starting with a lesser degree of freedom and ending with a greater degree of freedom provides efficient switching allocations and acknowledgements.Type: GrantFiled: February 3, 2009Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Alain Blanc, Rene Glaise, Francois Le Maut, Michel Poret
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Patent number: 8055984Abstract: A method for combining a simple forward error correction code i.e., a Hamming-like code with scrambling and descrambling functions is disclosed. Therefore, irrespective of the information to be transported, received data may be corrected, bit error spreading effects being handled, while providing desirable signal characteristics such as signal DC balance and enough signal transitions. The overhead introduced by the method is a modest increase over the original overhead of the 10 Gb Ethernet 64B/66B code.Type: GrantFiled: July 11, 2007Date of Patent: November 8, 2011Assignee: International Business Machines CorporationInventors: Rene Gallezot, Rene Glaise, Michel Poret
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Patent number: 7996747Abstract: A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable.Type: GrantFiled: November 3, 2006Date of Patent: August 9, 2011Assignee: International Business Machines CorporationInventors: Timothy Dell, Rene Glaise
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Patent number: 7839797Abstract: A method for controlling the flows of data packets that are switched or routed at nodes of high-speed communication networks is disclosed. According to the invention, resource metering units are assigned to resources shared between devices of the switch or router e.g., shared memories or link bandwidths. When the occupancy of a shared resource reaches a predetermined threshold, an event is generated and transmitted to devices sharing this resource. Furthermore, a periodic refresh of the overall flow control information is performed so that lost events are, however, eventually acted on. Thus, a new device may become active without perturbing the active flows after having gathered enough flow control information.Type: GrantFiled: September 17, 2007Date of Patent: November 23, 2010Assignee: International Business Machines CorporationInventors: Rene Gallezot, Rene Glaise, Francois Le Maut
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Patent number: 7787446Abstract: A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ‘PSNr’ of a last received in-sequence data packet and each highest packet sequence number ‘HPSNj’ received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number ‘PSNr’ to each highest packet sequence number ‘HPSNj’ when the number of data packets ‘WPC’ exceeds the predefined threshold value ‘WPCth’ a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.Type: GrantFiled: May 23, 2008Date of Patent: August 31, 2010Assignee: International Business Machines CorporationInventors: Francois Le Maut, Rene Glaise, Michel Poret, Rene Gallezot
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Patent number: 7773602Abstract: An embodiment of the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter has a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location, a controller, and a determination means coupled to a storing means and extracting means.Type: GrantFiled: May 20, 2008Date of Patent: August 10, 2010Assignee: International Business Machines CorporationInventors: Alain Blanc, Rene Glaise, Michel Poret, Rene Gallezot
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Patent number: 7769003Abstract: A high speed data packet switch comprising input and output ports and a switch fabric to link each input port to each output port wherein each connection between input and output ports comprises a dynamic buffer memory for storing at least one data packet for a minimum specified storing time is disclosed. When a data packet is received through an input port, it is written in all individual dynamic memory buffers connected to this input port so as to have a copy of the incoming data packet ready to go through any output port to support unicast, multicast and broadcast traffic. Given the architecture of the data packet switch and its control algorithm, dynamic memory buffers neither need to be refreshed nor their contents have to be restored after reading.Type: GrantFiled: September 10, 2007Date of Patent: August 3, 2010Assignee: International Business Machines CorporationInventors: Rene Glaise, Alain Blanc, Francois Le Maut, Michel Poret
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Patent number: 7706394Abstract: A system and a method to avoid packet traffic congestion in a shared-memory switch core, while dramatically reducing the amount of shared memory in the switch core and the associated egress buffers, is disclosed. According to the invention, the virtual output queuing (VOQ) of all ingress adapters of a packet switch fabric are collapsed into its central switch core to allow an efficient flow control. The transmission of packets from an ingress buffer to the switch core is subject to a mechanism of request/acknowledgment. Therefore, a packet is transmitted from a virtual output queue to the shared-memory switch core only if the switch core can actually forward it to the corresponding egress buffer. A token based mechanism allows the switch core to determine the egress buffer's level of occupation. Therefore, since the switch core knows the states of the input and output adapters, it is able to optimize packet switching and to avoid packet congestion.Type: GrantFiled: July 20, 2004Date of Patent: April 27, 2010Assignee: International Business Machines CorporationInventors: Alain Blanc, Rene Glaise, Francois Le Maut, Michel Poret
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Publication number: 20090141733Abstract: A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism. According to the method, an efficient set of virtual output queues (at most one virtual output queue per ingress adapter) is selected, while keeping the algorithm simple enough to allow its implementation in fast state machines. For determining a set of virtual output queues that are each authorized to send a packet, the algorithm is based upon degrees of freedom characterizing states of ingress and egress adapters. For example, the degree of freedom, derived from the collapsed virtual output queuing array, could represent the number of egress ports to which an ingress port may send packet, or the number of ingress ports from which an egress port may receive packets, at a given time.Type: ApplicationFiled: February 3, 2009Publication date: June 4, 2009Applicant: International Business Machines CorporationInventors: Alain Blanc, Rene Glaise, Francois Le Maut, Michel Poret
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Patent number: 7486683Abstract: A method for selecting packets to be switched in a collapsed virtual output queuing array (cVOQ) switch core, using a request/acknowledge mechanism. According to the method, an efficient set of virtual output queues (at most one virtual output queue per ingress adapter) is selected, while keeping the algorithm simple enough to allow its implementation in fast state machines. For determining a set of virtual output queues that are each authorized to send a packet, the algorithm is based upon degrees of freedom characterizing states of ingress and egress adapters. For example, the degree of freedom, derived from the collapsed virtual output queuing array, could represent the number of egress ports to which an ingress port may send packet, or the number of ingress ports from which an egress port may receive packets, at a given time.Type: GrantFiled: July 20, 2004Date of Patent: February 3, 2009Assignee: International Business Machines CorporationInventors: Alain Blanc, Rene Glaise, Francois Le Maut, Michel Poret
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Publication number: 20080267206Abstract: An embodiment of the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter has a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location, a controller, and a determination means coupled to a storing means and extracting means.Type: ApplicationFiled: May 20, 2008Publication date: October 30, 2008Inventors: Alain Blanc, Rene Glaise, Michel Poret, Rene Gallezot
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Patent number: 7430167Abstract: A method and a system to adapt the load balancing of the incoming traffic over the planes of a parallel packet switch (PPS) on the basis of the monitoring of requests and acknowledgments exchanged between ingress port adapters and arrays of collapsed virtual output queues (cVOQ) situated within the plane switch cores is disclosed. According to the invention, at least one counter is associated, in each ingress port-adapter, to each individual switching plane or device to be monitored. Each of these counters is incremented when a request is sent to the corresponding individual switching plane or device and decremented when an acknowledgment is received from this individual switching plane or device. When the range of values taken by the counters of a same ingress port-adapter reaches a predetermined threshold, less (or none) incoming traffic is further transmitted to the individual switching plane or device associated to the higher value counter. An alarm signal is possibly raised too e.g.Type: GrantFiled: September 10, 2004Date of Patent: September 30, 2008Assignee: International Business Machines CorporationInventors: Rene Glaise, Alain Blanc, Francois Le Maut, Michel Poret
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Publication number: 20080225854Abstract: A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ‘PSNr’ of a last received in-sequence data packet and each highest packet sequence number ‘HPSNj’ received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number ‘PSNr’ to each highest packet sequence number ‘HPSNj’ when the number of data packets ‘WPC’ exceeds the predefined threshold value ‘WPCth’ a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.Type: ApplicationFiled: May 23, 2008Publication date: September 18, 2008Applicant: International Business Machines CorporationInventors: Francois Le Maut, Rene Glaise, Michel Poret, Rene Gallezot
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Patent number: 7403536Abstract: A method to resequence packets includes sequentially allocating in each source ingress adapter a packet rank to each packet received within each source ingress adapter. In each destination egress adapter, each ranked data packet is stored at a respective buffer address of an egress buffer. The respective buffer addresses of data packets received by a same source ingress adapter with a same priority level and switched through a same switching plane are linked in a same linked-list. The respective buffer addresses are preferably linked by their order of use in the egress buffer, and thus each linked-list is having a head list pointing to the oldest buffer address. The linked-lists are sorted into subsets including those linked-lists linking the respective buffer addresses of data packets received by a same source ingress adapter with a same priority level.Type: GrantFiled: November 26, 2003Date of Patent: July 22, 2008Assignee: International Business Machines CorporationInventors: Alain Blanc, Rene Glaise, Michel Poret, Daniel Wind
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Publication number: 20080172589Abstract: A method for combining a simple forward error correction code i.e., a Hamming-like code with scrambling and descrambling functions is disclosed. Therefore, irrespective of the information to be transported, received data may be corrected, bit error spreading effects being handled, while providing desirable signal characteristics such as signal DC balance and enough signal transitions. The overhead introduced by the method is a modest increase over the original overhead of the 10 Gb Ethernet 64B/66B code.Type: ApplicationFiled: July 11, 2007Publication date: July 17, 2008Inventors: Rene Gallezot, Rene Glaise, Michel Poret
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Patent number: 7400629Abstract: A system for resequencing data packets is disclosed. In a preferred embodiment, the system operates in a parallel packet switch architecture having at least one egress adapter arranged to receive data packets issued from a plurality of ingress adapters and switched through a plurality of independent switching planes. Each received data packet belongs to one sequence of data packets among a plurality of sequences where the data packets are numbered with a packet sequence number (PSN) assigned according to at least a priority level of the data packet. Each data packet received by the at least one egress adapter is further having a source identifier to identify the ingress adapter from which it is issued. The system for restoring the sequences of the received data packets operates within the egress adapter and comprises buffer for temporarily storing each received data packet at an allocated packet buffer location.Type: GrantFiled: November 26, 2003Date of Patent: July 15, 2008Assignee: International Business Machines CorporationInventors: Alain Blanc, Rene Glaise, Michel Poret, Rene Gallezot
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Patent number: 7391766Abstract: A system for controlling egress buffer saturation includes, for each data packet flow, a comparator for comparing the number of data packets ‘WPC’ temporarily stored within an egress buffer to a predefined threshold value ‘WPCth’. The packet sequence number ‘PSNr’ of a last received in-sequence data packet and each highest packet sequence number ‘HPSNj’ received through respective ones of the plurality of switching planes is stored. By comparing the last received in-sequence packet sequence number ‘PSNr’ to each highest packet sequence number ‘HPSNj’ when the number of data packets ‘WPC’ exceeds the predefined threshold value ‘WPCth’ a determination as to which switching plane(s), among the plurality of switching planes, to unstop the flow of data packets can be made.Type: GrantFiled: November 26, 2003Date of Patent: June 24, 2008Assignee: International Business Machines CorporationInventors: Francois Le Maut, Rene Glaise, Michel Poret, Rene Gallezot
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Publication number: 20080109707Abstract: A Forward Error Correction (FEC) code compatible with the self-synchronized scrambler used by the 64B/66B encoding standard for transmission on Serializer/Deserializer (SerDes) communications channel links. The FEC code allows encoding and decoding to occur before and after scrambling, respectively, so as to preserve the properties of the scrambling operation on the transmitted signal. The code allows the correction of any single transmission error in spite of the multiplication by three of all transmission errors due to the 64B/66B scrambling process. A Hamming code is combined with a Bit Interleaved Parity code of degree n (BIP-n). These two codes provide for protection both for an error anywhere in the maximum length of the packet as well as for an error replicated two or three times by the descrambling process. All single bit errors, whether multiplied or not, have unique syndromes and are therefore easily correctable.Type: ApplicationFiled: November 3, 2006Publication date: May 8, 2008Inventors: Timothy Dell, Rene Glaise
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Patent number: 7324460Abstract: A method for controlling the flows of data packets that are switched or routed at nodes of high-speed communication networks is disclosed. According to the invention, resource metering units are assigned to resources shared between devices of the switch or router e.g., shared memories or link bandwidths. When the occupancy of a shared resource reaches a predetermined threshold, an event is generated and transmitted to devices sharing this resource. Furthermore, a periodic refresh of the overall flow control information is performed so that lost events are, however, eventually acted on. Thus, a new device may become active without perturbing the active flows after having gathered enough flow control information.Type: GrantFiled: September 29, 2003Date of Patent: January 29, 2008Assignee: International Business Machines CorporationInventors: Rene Gallezot, Rene Glaise, Francois Le Maut