Abstract: A method and apparatus for performing encoding and decoding of bit chain data packets conveying errors which do not spread on more than n bits, at very high speed are here disclosed. The matrix of the corresponding Systematic code is built using p×p matrix blocks comprising elements of the galois field GF, generated by an irreducible generator polynomial of degree p, p being greater or equal to n. With the preferred embodiment of the invention, the decoding operation includes an error detection which distinguishes errors between correctable and non correctable errors. The errors limited inside fixed size bursts are 100% corrected if confined to one burst and are all detected if spread on two bursts. The ASIC implementation of the decoding method of the invention requires only a combinatorial logic. The method and apparatus of the invention allows a 21 bit error code applied to a typical 512 bit data packets transported on 8B/10B coded 2.

Abstract: The present invention describes direct decoding of Error Correction Codes (ECC) such as, for example, FIRE and similar codes, and detecting and correcting errors occurring in burst, without requiring any pattern shift or sequential logic. According to the present invention, the syndrome of a code generated with a degree-d polynomial is split into sub-syndromes that are combined to form at least one kind of error pattern from which an error pattern is picked. If the picked error pattern does not correspond to an uncorrectable error and errors are not confined within first d bits, one of the sub-syndromes is selected according to the correction mode. The ranks of this selected sub-syndrome and picked error pattern in the Galois field generated by a factor of the degree-d polynomial are determined.

Abstract: The present invention discloses CRC checking 'N-bit at a time' of data frames of lengths not necessarily in a multiple of the N-bit. While receiving the data frame, the data frame length is extracted from the protocol header and a misalignment is computed versus the 'N-bit at a time' value. Simultaneously, CRC is computed on each received N-bit of the data frame and an FCS register is updated. At each cycle, a checking is performed to know whether the data frame length has been extracted from the protocol header. While the data frame length is not yet known and more bits are left to process, the data frame is continued to be received and computed 'N-bit at a time'. When the data frame length is known and no more bits are to be processed, the current value of the FCS register is compared to a pre-stored vector corresponding to the misalignment. If a match occurs, checking of the data frame passes and the data frame is accepted.

Abstract: The invention provides a method and system for accessing ports of a very high-speed, fixed-size cell switch fabric. It is aimed at permitting a tradeoff between the overall number of I/Os required to access all the switch ports, that must stay within the board and modules packaging constraints and the maximum speed at which each individual wire, making up ports, may be toggled while not violating any of the speed limitation imposed by the transmission medium (board wiring) or the module interface devices; i.e., receivers and drivers. This is achieved by eliminating the need of having extra control signals, thus, greatly easing the requirement for module and board I/Os. Then, synchronization is obtained from in-band information transported by fixed-size idle logical units from a robust protocol based on two CRCs. The acquisition of synchronization does not require any particular training sequence and is conducted by the receiving device component only which retrieves computed delimiters on which it locks.

Abstract: A high speed data packet switch comprising input and output ports and a switch fabric to link each input port to each output port wherein each connection between input and output ports comprises a dynamic buffer memory for storing at least one data packet for a minimum specified storing time is disclosed. When a data packet is received through an input port, it is written in all individual dynamic memory buffers connected to this input port so as to have a copy of the incoming data packet ready to go through any output port to support unicast, multicast and broadcast traffic. Given the architecture of the data packet switch and its control algorithm, dynamic memory buffers neither need to be refreshed nor their contents have to be restored after reading.

Abstract: A backplane system allowing a very large number of interconnections between high-connectivity printed circuit boards and a backplane is disclosed. The backplane is fragmented into a plurality of backplane parts that comprise connectors on their edges to mate connectors arranged on the high-connectivity printed circuit boards. These backplane parts may also include other connectors on their edges to couple to extension printed circuit boards requiring less interconnections or cables. Interposers can be used to link several backplane parts and provide enhanced air circulation.

Abstract: A general way of performing a Cyclic Redundancy Check (CRC) calculation, N-bit at a time, is disclosed. CRC calculation is based on a generator polynomial G(x) of degree d so that all results always fit a d-bit wide Field Check Sequence (FCS). The generator polynomial allows forming a multiplicative cyclic group comprised of d-bit wide binary vectors. The iterative calculation method assumes that each new N-bit chunk of data bits, picked from the binary string of data bits, is divided, modulo the generator polynomial G(x), so that to obtain a d-bit wide division result while a current value of the d-bit wide FCS is displaced in the multiplicative cyclic group, of a value corresponding to N. Then, the d-bit wide division result and the displaced d-bit wide FCS are added to become the new current FCS. The above steps are re-executed until no data bits are left thus, getting the final result of the CRC calculation which can be used either for checking or generation of FCS.

Abstract: A single check field can be generated and appended to packets prior to a switching or other operation to support post-operation verification that protected fields were not altered during the operation and that the post-operation packet sequence matches the pre-operation packet sequence. The check field requires the use of nominally-synchronized packet counters at the check field generating system and at the verification system. The check field is generated by performing a CRC calculation on the protected fields of the packet. The CRC result is combined with the current packet count to obtain the final check field, which is appended to the packet. At the verification system, a CRC calculation is performed on the protected fields of the packet, included the appended final check field. This provides an interim check result which is compared to the current packet count at the verification system. A non-null compare result is indicative of an error condition.

Abstract: The present method and apparatus provide a searching operation of variable bit chain keys, the implementation being possible in software and cost effective in hardware. When implemented in the network routers, this solution sustains performance required for routing IPV4 OR IPV6 datagrams node insert and delete operations maintain the data base with no need for further garbage collection. The Extended patricia tree data structure of the invention the determination in advance of the process time and the storage resources which will be used. Variable bit chain keys padded with zeros and their prefix length are stored in the extended patricia tree. A search is performed in two parts, a first up-down displacement in the tree followed by a down-up displacement to find the key stored in one node in the tree having the longest matching prefix with the key to be searched.

Abstract: A method and system for optimizing transmission links bandwidth utilization in an Asynchronous Transfer Mode (ATM) packet switching network including switching nodes interconnected by high speed transmission links, said network being made to transport user data traffic including PTM traffic organized into variable length packets, each packet comprising a variable length data payload and an original fixed length PTM packet header.

Abstract: A method and an apparatus to calculate the CRC-32 (Cyclic Redundancy Checking) codes of a bit stream while improving the process time and simple to implement. The CRC-32 calculation is used for FCS (Frame Check Sequence) error checking code of bit stream messages sent over a fixed size packet networks when the high speeds require reducing the processing time in the network access nodes. This CRC-32 calculation is also used for FCS checking in the network equipment receiving said packetized bit stream messages. This invention applies particularly to messages conveyed via AAL5 type cells in ATM networks. The CRC-32 per byte computation of the prior art is replaced by a simple per byte CRC-R computation followed by a one pass CRC-32 computation of the R bit stream, result of the CRC-R computation.

Abstract: A method and an apparatus for searching a bit field whose significant bits comprise two contiguous bit fields such as the VPI/VCI bit fields of an ATM cell header. The invention uses a hash key based on CRC-n calculated on the bit field to be searched. One m bit field part of the significant bits of the bit field to be searched can be concatenated with the CRC-n to form a double hash key. It appears that, L being the total of the two contiguous bit field lengths, if L=m=n+p, p being greater or equal to 4, the scattering of data to be searched is perfect. The method comprised a first step of pointing to a first address with the hash (or double hash) key and reading a maximum of 2.sup.p addresses before reaching the addresses containing the bit field to be searched.

Abstract: A process and an apparatus to calculate the FCS (Frame Check Sequence) error checking code of packets payload sent over a fixed size packet networks in a network equipment sending said packets and to check said FCS in the network equipment receiving said packet; this invention applies to calculations of FCS based on CRC (Cyclic Redundancy Checking) codes generated by the polynomial generator of degree 10, G(X)=X.sup.10 +X.sup.9 +X.sup.5 +X.sup.4 +X+1. Particularly, this invention is for use in the ATM layer of ATM nodes processing OA&M and AAL3/4 ATM cells. The solution consists in using the calculation of the FCS based on the CRC code generated by the polynomial generator of degree 9, X.sup.9 +X.sup.4 +1 and simple operations. The calculation and the checking of the FCS is simple and thus the performance are improved authorizing the support of higher speed network lines.

Abstract: A method and an apparatus for shaping the output traffic in the transmit part of a network node adapter. The network node supports fixed length cell switching user information traffic between a source unit and a destination unit. The method and apparatus use two lookup tables called an active and a standby calendar per output line. Each entry in the calendars represents the position of one cell in the output cell stream. Three parameters tables are used to store the information on user traffic in the descending order of the user bandwidth share negotiated at traffic establishment time for the calendars. The active calendar is continuously read by a transmit device and the corresponding cells are sent onto the output line. Under control of a control device, a placement device places entries in the standby calendar reserved as changes occur in the traffic. Once filled up, the standby calendar is swapped to the active calendar and is read by the transmit device.

Abstract: A circuit arrangement synchronizes data transfers between a first device and a second device operating at different data rates. The circuit arrangement is comprised of a plurality of registers for storing data received from a device with the higher data rate. A scan logic circuit counts strobe pulses provided by the device with the higher data rate when data is available on its output bus. Selected counts from the scan logic circuit cause data on the output bus to be sequentially transferred into the plurality of registers. Strobe latch logic keeps track of the loading sequence and, in response thereto, select logic and gate arrangement causes the content of a selected register to be transferred to an output register at each clock signal of the slower device.

Abstract: In intermediate network nodes of high speed packet switching networks, when a message is modified, the invention proposes a method and an apparatus for calculating a modified FCS error code. Using the properties of calculations in the Galois Field, the implementation of the invention, specially in the intermediate Frame Relay network nodes, is reduced to a plurality of simple well known operators (90, 100, 120, 30); the implementation of the invention allows the usage of a plurality of small lookup tables (60, 70, 80, 110) as desired and thus avoiding large amounts of storage resources.

Abstract: A method and an apparatus for calculating and checking the Frame Check Sequence (FCS) of a message comprising a sequence of data bytes. A Cyclic Redundancy Code (CRC) is used to generate the FCS at one end and check the message at the other end. For each new byte of the sequence of data bytes, the current FCS, which is a vector of the Galois Field is multiplied by .alpha..sup.8, another vector of the Galois Field.

Abstract: A memory interface mechanism is driven from the memory controller side which comprises lines which are shared by the memory user devices and lines which are specific to the memory user devices. The shared lines are the address and data bus lines the byte select lines, the data and address clock lines and the last operation line. The specific lines are the request lines, the address user indicator lines and data user indicator lines. A user initiates a memory operation by activating its request line and then waits for the activation by the memory interface control circuit for the activation of the address and data user indicator lines. The user controls the address and data transfer count and ends the transfer by activating the last operation line. Then it waits for the deactivation by the memory controller of the address and data user indicator lines to present a new request, if any. Thus the memory transfer is memory driven which allows full advantage to be taken of a page mode facility of the memory.

Abstract: An apparatus and method for correcting data words from a memory is provided in which coded data is divided into a plurality of multi-bit packages of b bits each. The coded data comprises n-bit words with r error correcting code bits and n-r data bits. The invention is capable of correcting one package which has suffered at least one hard failure and a single soft error located in a different package. The invention involves the use of an error correcting code which gives a first syndrome when the data word has suffered a first error coming from at least one error in a first package and a single error in a different second package, which also gives a second syndrome when the data word has suffered a second error coming from at least one error in the above first package, and a single error in a third package. The error correcting code is such that equality of the first and second syndromes results in the equality of the first and second errors.

Abstract: Arrangement allowing an input bucket brigade (BBD) stage to feed several other BBD stages in parallel with no loss of the signal transferred from the input stage to the subsequent ones. An input voltage corresponding to a charge quantity is stored in the second capacitor of the input BBD stage. The drain of the output transistor of the input stage is connected to a first BBD stage wherein the first capacitor is connected to the source electrode of the first transistor of a second BBD stage. The first transistors of both stages are controlled by the same clock pulses. When these transistors are turned on, the capacitors connected thereto are in series with the second capacitor of the input stage. Consequently, the same current will flow through these capacitors, which will thus store the same charges so that the charge representing the input voltage will be reproduced in the first capacitors of the two BBD stages connected to the input stage.