Patents by Inventor Rennier Rodriguez

Rennier Rodriguez has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200135686
    Abstract: The present disclosure is directed to a semiconductor die with multiple contact pads electrically coupled to a single lead via a single wire, and methods for fabricating the same. In one or more embodiments, multiple contact pads are electrically coupled to each other by a plurality of conductive layers stacked on top of each other. The uppermost conductive layer is then electrically coupled to a single lead via a single wire.
    Type: Application
    Filed: October 25, 2019
    Publication date: April 30, 2020
    Inventors: Rennier RODRIGUEZ, Rammil SEGUIDO, Raymond Albert NARVADEZ, Michael TABIERA
  • Patent number: 10615104
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Grant
    Filed: October 8, 2018
    Date of Patent: April 7, 2020
    Assignee: STMicroelectronics, Inc.
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
  • Patent number: 10535588
    Abstract: The present disclosure is directed to a die having a metallized sidewall and methods of manufacturing the same. A contiguous metal layer is applied to each edge of a backside of a wafer. The wafer is cut at a base of a plurality of channels formed in the backside to create individual die each having a flange that is part of a sidewall of the die and includes a portion that is covered by the metal layer. When an individual die is coupled to a die pad, a semiconductive glue bonds the metal layer on the sidewall and a backside of the die to the die pad, which decreases the risk of delamination along the sides of the die. The flange also prevents the glue from contacting the active side of the die by acting as a barrier against adhesive creep of the glue up the sidewall of the die.
    Type: Grant
    Filed: January 18, 2017
    Date of Patent: January 14, 2020
    Assignee: STMicroelectronics, Inc.
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo
  • Publication number: 20190267310
    Abstract: The present disclosure is directed to a lead frame including a die pad with cavities, and methods for attaching a semiconductor die to the lead frame. The cavities allow for additional adhesive to be formed on the die pad at the corners of the semiconductor die, and prevent the additional adhesive from overflowing on to active areas of the semiconductor die.
    Type: Application
    Filed: February 1, 2019
    Publication date: August 29, 2019
    Inventors: Rennier RODRIGUEZ, Maiden Grace MAMING, Jefferson TALLEDO
  • Publication number: 20190148271
    Abstract: The present disclosure is directed to a leadframe package having leads with protrusions on an underside of the leadframe. The protrusions come in various shapes and sizes. The protrusions extend from a body of encapsulant around the leadframe to couple to surface contacts on a substrate. The protrusions have a recess that is filled with encapsulant. Additionally, the protrusions may be part of the lead or may be a conductive layer on the lead. In some embodiments a die pad of the leadframe supporting a semiconductor die also has a protrusion on the underside of the leadframe. The protrusion on the die pad has a recess that houses an adhesive and at least part of the semiconductor die. The die pad with a protrusion may include anchor locks at the ends of the die pad to couple to the encapsulant.
    Type: Application
    Filed: January 16, 2019
    Publication date: May 16, 2019
    Inventors: Rennier RODRIGUEZ, Raymond Albert NARVADEZ, Ernesto ANTILANO, JR.
  • Publication number: 20190139875
    Abstract: The present disclosure is directed to a flat no-lead semiconductor package with a surfaced mounted structure. An end portion of the surface mounted structure includes a recessed member so that the surface mounted structure is coupled to leads of the flat no-lead semiconductor package through, among others, the sidewalls of the recessed members.
    Type: Application
    Filed: November 9, 2017
    Publication date: May 9, 2019
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Maiden Grace Maming
  • Publication number: 20190096788
    Abstract: A semiconductor package includes a lead frame, a die, a discrete electrical component, and electrical connections. The lead frame includes leads and a die pad. Some of the leads include engraved regions that have recesses therein and the die pad may include an engraved region or multiple engraved regions. Each engraved region is formed to contain and confine a conductive adhesive from flowing over the edges of the engraved leads or the die pad. The boundary confines the conductive adhesive to the appropriate location on the engraved lead or the engraved die pad when being placed on the engraved regions. By utilizing a lead frame with engraved regions, the flow of the conductive adhesive or the wettability of the conductive adhesive can be contained and confined to the appropriate areas of the engraved lead or engraved die pad such that a conductive adhesive does not cause cross-talk between electrical components within a semiconductor package or short circuiting within a semiconductor package.
    Type: Application
    Filed: September 22, 2017
    Publication date: March 28, 2019
    Inventors: Rennier Rodriguez, Bryan Christian Bacquian, Maiden Grace Maming, David Gani
  • Publication number: 20190043790
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Application
    Filed: October 8, 2018
    Publication date: February 7, 2019
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
  • Patent number: 10109563
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Grant
    Filed: January 5, 2017
    Date of Patent: October 23, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
  • Publication number: 20180204786
    Abstract: The present disclosure is directed to a die having a metallized sidewall and methods of manufacturing the same. A contiguous metal layer is applied to each edge of a backside of a wafer. The wafer is cut at a base of a plurality of channels formed in the backside to create individual die each having a flange that is part of a sidewall of the die and includes a portion that is covered by the metal layer. When an individual die is coupled to a die pad, a semiconductive glue bonds the metal layer on the sidewall and a backside of the die to the die pad, which decreases the risk of delamination along the sides of the die. The flange also prevents the glue from contacting the active side of the die by acting as a barrier against adhesive creep of the glue up the sidewall of the die.
    Type: Application
    Filed: January 18, 2017
    Publication date: July 19, 2018
    Inventors: Rennier RODRIGUEZ, Aiza Marie AGUDON, Jefferson TALLEDO
  • Publication number: 20180190575
    Abstract: The present disclosure is directed to a leadframe package having leads with protrusions on an underside of the leadframe. The protrusions come in various shapes and sizes. The protrusions extend from a body of encapsulant around the leadframe to couple to surface contacts on a substrate. The protrusions have a recess that is filled with encapsulant. Additionally, the protrusions may be part of the lead or may be a conductive layer on the lead. In some embodiments a die pad of the leadframe supporting a semiconductor die also has a protrusion on the underside of the leadframe. The protrusion on the die pad has a recess that houses an adhesive and at least part of the semiconductor die. The die pad with a protrusion may include anchor locks at the ends of the die pad to couple to the encapsulant.
    Type: Application
    Filed: January 5, 2017
    Publication date: July 5, 2018
    Inventors: Rennier Rodriguez, Raymond Albert Narvadez, Ernesto Antilano, JR.
  • Publication number: 20180190576
    Abstract: The present disclosure is directed to a leadframe having a recess in a body of the leadframe to collect glue overflowing from the manufacturing process of coupling a semiconductor die to the leadframe. The recess extends beneath an edge of the semiconductor die so that any tendency of the glue to adhere to the semiconductor die is counteracted by a tendency of the glue to adhere to a wall of the recess and at least partially fill the volume of the recess. In addition, the recess for collecting adhesive may also form a mold lock on an edge of the leadframe, the mold lock providing a more durable connection between the leadframe and an encapsulant during physical and temperature stresses.
    Type: Application
    Filed: January 5, 2017
    Publication date: July 5, 2018
    Inventors: Rennier Rodriguez, Aiza Marie Agudon, Jefferson Talledo, Moonlord Manalo, Ela Mia Cadag, Rammil Seguido
  • Patent number: 9953933
    Abstract: A semiconductor package includes a substrate, a die, an insulating die attach film, a dummy die, a conductive layer, and an electrically conductive molding compound or encapsulant. The first surface of the substrate includes a plurality of internal leads, and the second surface of the substrate includes a plurality of external electrically conductive pads and an electrically conductive ground terminal. A non-conductive flow over wire die attach film is placed to surround and encase the die. The dummy die overlies the die and a conductive layer overlies the dummy die. The electrically conductive molding compound is formed to encase the various components of the semiconductor device. The electrically conductive molding compound is electrically coupled to the electrically conductive ground terminal and the conductive layer forming an EMI shield for the die in the package.
    Type: Grant
    Filed: March 30, 2017
    Date of Patent: April 24, 2018
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Aaron Cadag, Rennier Rodriguez, Ela Mia Cadag
  • Publication number: 20170263566
    Abstract: A method for making shielded integrated circuit (IC) packages includes providing spaced apart IC dies carried by a substrate and covered by a common encapsulating material, and cutting through the common encapsulating material between adjacent IC dies to define spaced apart IC packages carried by the substrate. An electrically conductive layer is positioned over the spaced apart IC packages and fills spaces between adjacent IC packages. The method further includes cutting through the electrically conductive layer between adjacent IC packages and through the substrate to form the shielded IC packages.
    Type: Application
    Filed: March 14, 2016
    Publication date: September 14, 2017
    Inventors: Rennier RODRIGUEZ, Frederick ARELLANO, Aiza Marie AGUDON
  • Patent number: 9761538
    Abstract: A method for making shielded integrated circuit (IC) packages includes providing spaced apart IC dies carried by a substrate and covered by a common encapsulating material, and cutting through the common encapsulating material between adjacent IC dies to define spaced apart IC packages carried by the substrate. An electrically conductive layer is positioned over the spaced apart IC packages and fills spaces between adjacent IC packages. The method further includes cutting through the electrically conductive layer between adjacent IC packages and through the substrate to form the shielded IC packages.
    Type: Grant
    Filed: March 14, 2016
    Date of Patent: September 12, 2017
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Rennier Rodriguez, Frederick Arellano, Aiza Marie Agudon