Patents by Inventor Rex Young
Rex Young has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20210263788Abstract: Technology is disclosed for processing in a computer program a request received by a service virtual machine (SVM).Type: ApplicationFiled: May 5, 2021Publication date: August 26, 2021Inventor: Rex Young
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Patent number: 11060127Abstract: An assembly for preparing a specimen is provided that may be configured to determine the presence of at least one microorganism specie in the specimen. The assembly may include a pipette configured to acquire a specimen from a sample and an imaging cartridge configured to be in fluid communication with the pipette. The imaging cartridge and the pipette may be configured to be irreversibly coupled such that the specimen is bio-contained within the imaging cartridge and the pipette when the imaging cartridge and pipette are coupled together. Associated methods of use are also provided.Type: GrantFiled: March 7, 2019Date of Patent: July 13, 2021Assignee: BECTON, DICKINSON AND COMPANYInventors: Alexander George Lastovich, Anita Quinn, Pauline Elizabeth Bell, James Lee Schram, Rex Young Nielson, Jason Paul Hayes, Matthew James Springer, Lincoln Belcourt, Matthew Daniel Solomon
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Patent number: 11036565Abstract: Technology is disclosed for processing in a computer program a request received by a service virtual machine (SVM).Type: GrantFiled: May 30, 2014Date of Patent: June 15, 2021Inventor: Rex Young
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Publication number: 20190271023Abstract: An assembly for preparing a specimen is provided that may be configured to determine the presence of at least one microorganism specie in the specimen. The assembly may include a pipette configured to acquire a specimen from a sample and an imaging cartridge configured to be in fluid communication with the pipette. The imaging cartridge and the pipette may be configured to be irreversibly coupled such that the specimen is bio-contained within the imaging cartridge and the pipette when the imaging cartridge and pipette are coupled together. Associated methods of use are also provided.Type: ApplicationFiled: March 7, 2019Publication date: September 5, 2019Inventors: Alexander George Lastovich, Anita Quinn, Pauline Elizabeth Bell, James Lee Schram, Rex Young Nielson, Jason Paul Hayes, Matthew James Springer, Lincoln Belcourt, Matthew Daniel Solomon
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Patent number: 10273523Abstract: An assembly for preparing a specimen is provided that may be configured to determine the presence of at least one microorganism specie in the specimen. The assembly may include a pipette configured to acquire a specimen from a sample and an imaging cartridge configured to be in fluid communication with the pipette. The imaging cartridge and the pipette may be configured to be irreversibly coupled such that the specimen is bio-contained within the imaging cartridge and the pipette when the imaging cartridge and pipette are coupled together. Associated methods of use are also provided.Type: GrantFiled: April 28, 2014Date of Patent: April 30, 2019Assignee: Becton, Dickinson and CompanyInventors: Alexander George Lastovich, Anita Quinn, Pauline Elizabeth Bell, James Lee Schram, Rex Young Nielson, Jason Paul Hayes, Matthew James Springer, Lincoln Belcourt, Matthew Daniel Solomon
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Publication number: 20160076072Abstract: An assembly for preparing a specimen is provided that may be configured to determine the presence of at least one microorganism specie in the specimen. The assembly may include a pipette configured to acquire a specimen from a sample and an imaging cartridge configured to be in fluid communication with the pipette. The imaging cartridge and the pipette may be configured to be irreversibly coupled such that the specimen is bio-contained within the imaging cartridge and the pipette when the imaging cartridge and pipette are coupled together. Associated methods of use are also provided.Type: ApplicationFiled: April 28, 2014Publication date: March 17, 2016Applicant: Becton, Dickinson and CompanyInventors: Alexander George Lastovich, Anita Quinn, Pauline Elizabeth Bell, James Lee Schram, Rex Young Nielson, Jason Paul Hayes, Matthew James Springer, Lincoln Belcourt, Matthew Daniel Solomon
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Publication number: 20140282549Abstract: Technology is disclosed for processing in a computer program a request received by a service virtual machine (SVM).Type: ApplicationFiled: May 30, 2014Publication date: September 18, 2014Inventor: Rex Young
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Publication number: 20090307712Abstract: An actor virtual machine is described. In various embodiments, the actor virtual machine (AVM) implements a practicable message-passing model in a computer programming language that supports components and concurrent execution. The model includes receiving by a first actor virtual machine a message from a first component wherein the received message includes no addressing information; identifying from a stored routing rule a second component to which the received message should be forwarded; and forwarding the received message to the identified second component, wherein the first actor virtual machine, the first component, and the second component are all components of an executing software application.Type: ApplicationFiled: June 9, 2008Publication date: December 10, 2009Inventor: Rex Young
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Publication number: 20090130808Abstract: A method of fabricating a flash memory includes successively forming a floating gate insulating layer, a floating gate material layer, a dielectric layer, a control gate material layer, a silicide layer, and a hard mask layer on a semiconductor substrate, patterning the hard mask layer, removing portions of the silicide layer, the control gate material layer, the dielectric layer, and the floating gate material layer not covered by the hard mask layer to form a stacked structure, forming a silicon cap layer covering the surface of the stacked structure, and performing a thermal process.Type: ApplicationFiled: November 20, 2007Publication date: May 21, 2009Inventors: Chao-Yuan Lo, Rex Young, Pin-Yao Wang
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Publication number: 20090075443Abstract: A method of fabricating a flash memory includes providing a substrate with a mask layer thereon, forming pluralities of shallow trenches in the substrate, forming a first oxide layer on the substrate and in the shallow trenches, removing a portion of the first oxide layer above the mask layer, forming a second oxide layer on the mask layer and the first oxide layer, wherein the first and second oxide layers have different etching ratios, removing a portion of the second oxide layer positioned above the mask layer so that an STI is formed with the first and the second oxide layers in each shallow trench, removing the mask layer to form recess portions between adjacent STIs, and filling the recess portions with a conductive layer to form floating gates in the recess portions.Type: ApplicationFiled: December 24, 2007Publication date: March 19, 2009Inventors: Chia-Che Hsu, Rex Young, Pin-Yao Wang
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Patent number: 7445998Abstract: A method for fabricating a semiconductor device is described. The method includes providing a substrate having a trench therein, and a trench device in the trench. The trench device includes two gate structures disposed on the sidewalls of the trench, a doped region in the substrate between the gate structures and an inter-gate dielectric layer disposed on the surface of the gate structures. A thermal treatment process in a nitrogen-containing ambient is performed to remove the native oxide layer formed on the surface of the doped region. Then, a conductive layer is formed to fill in the trench.Type: GrantFiled: January 7, 2008Date of Patent: November 4, 2008Assignee: Powerchip Semiconductor Corp.Inventors: Rex Young, Pin-Yao Wang
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Publication number: 20080224202Abstract: A non-volatile memory includes a substrate, a number of isolation layers, a number of active layers, a number of floating gates, a number of control gates and a number of doped regions. The active layers are disposed in the substrate between the isolation layers, and the top surface of the active layer is higher than that of the isolation layer. The active layers and the isolation layers are arranged in parallel to each other and extend in the first direction. The control gates are disposed in the substrate. The control gates are arranged in parallel and extend in the second direction which crosses the first direction. The floating gates are disposed between the active layers and the control gates. The doped regions are disposed in the active layers between the control gates.Type: ApplicationFiled: May 29, 2008Publication date: September 18, 2008Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Rex Young, Pin-Yao Wang
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Publication number: 20080153289Abstract: A method for manufacturing a semiconductor device is disclosed. The method is suitable for a substrate having a first conducting structure and a first dielectric layer, wherein the dielectric layer covers the first conductive structure. The method includes the steps of forming a second conductive structure over the substrate adjacent to the first conductive structure. Then, the size of the second conductive structure is reduced so that a top surface of the second conductive structure is relatively lower than that of the first conductive structure. Thereafter, a second dielectric layer is formed over the substrate to cover the first and the second conductive structure. A via is formed in the second dielectric layer to expose the top surface of the first conductive structure. Finally, a via plug is formed in the via.Type: ApplicationFiled: March 4, 2008Publication date: June 26, 2008Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Min-San Huang, Dah-Chuan Chen, Rex Young
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Patent number: 7368373Abstract: A method for manufacturing a semiconductor device is disclosed suitable for a substrate having a first conducting structure and a first dielectric layer, wherein the dielectric layer covers the first conductive structure. The method includes the steps of forming a second conductive structure over the substrate adjacent to the first conductive structure. Then, the size of the second conductive structure is reduced so that a top surface of the second conductive structure is relatively lower than that of the first conductive structure. Thereafter, a second dielectric layer is formed over the substrate to cover the first and the second conductive structure. A via is formed in the second dielectric layer to expose the top surface of the first conductive structure. Finally, a via plug is formed in the via.Type: GrantFiled: August 29, 2005Date of Patent: May 6, 2008Assignee: Powerchip Semiconductor Corp.Inventors: Min-San Huang, Dah-Chuan Chen, Rex Young
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Publication number: 20080102580Abstract: A method for fabricating a semiconductor device is described. The method includes providing a substrate having a trench therein, and a trench device in the trench. The trench device includes two gate structures disposed on the sidewalls of the trench, a doped region in the substrate between the gate structures and an inter-gate dielectric layer disposed on the surface of the gate structures. A thermal treatment process in a nitrogen-containing ambient is performed to remove the native oxide layer formed on the surface of the doped region. Then, a conductive layer is formed to fill in the trench.Type: ApplicationFiled: January 7, 2008Publication date: May 1, 2008Applicant: POWERCHIP SEMICONDUCTOR CORP.Inventors: Rex Young, Pin-Yao Wang
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Patent number: 7354851Abstract: A method for fabricating a semiconductor device is described. The method includes providing a substrate having a trench therein, and a trench device in the trench. The trench device includes two gate structures disposed on the sidewalls of the trench, a doped region in the substrate between the gate structures and an inter-gate dielectric layer disposed on the surface of the gate structures. A thermal treatment process in a nitrogen-containing ambient is performed to remove the native oxide layer formed on the surface of the doped region. Then, a conductive layer is formed to fill in the trench.Type: GrantFiled: July 22, 2005Date of Patent: April 8, 2008Assignee: Powerchip Semiconductor Corp.Inventors: Rex Young, Pin-Yao Wang
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Patent number: 7316956Abstract: A method for fabricating a wire with silicide is disclosed. First, a conductive layer is formed on a substrate. And, a hard mask layer is formed on the conductive layer. Then, the hard mask layer is used as a mask to remove a portion of the conductive layer. Afterwards, a spacer is formed on the sidewalls of the conductive layer and the hard mask layer. Afterwards, the hard mask layer is removed. Next, a silicide is formed on the conductive layer.Type: GrantFiled: November 3, 2005Date of Patent: January 8, 2008Assignee: Powerchip Semiconductor Corp.Inventors: Rex Young, Liang-Chuan Lai
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Patent number: D564122Type: GrantFiled: March 24, 2006Date of Patent: March 11, 2008Assignee: The L.D. Kichler Co.Inventor: Rex Young
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Patent number: D575438Type: GrantFiled: November 14, 2007Date of Patent: August 19, 2008Assignee: The L.D. Kichler Co.Inventor: Rex Young
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Patent number: D577849Type: GrantFiled: March 9, 2007Date of Patent: September 30, 2008Assignee: The L.D. Kichler Co.Inventor: Rex Young