Abstract: A non-volatile memory includes a substrate, a plurality of isolation layers, a plurality of active layers, a plurality of floating gates, a plurality of control gates and a plurality of doped regions. The active layers are disposed in the substrate between the isolation layers, and the top surface of the active layer is higher than that of the isolation layer. The active layers and the isolation layers are arranged in parallel to each other and extend in the first direction. The control gates are disposed in the substrate. The control gates are arranged in parallel and extend in the second direction which crosses the first direction. The floating gates are disposed between the active layers and the control gates. The doped regions are disposed in the active layers between the control gates.

Abstract: A method for manufacturing an anti-punch through semiconductor device is described. The method is applied to a substrate having a plurality of device isolation structures in parallel arrangements and the upper surface of the device isolation structures is protruded from the surface of the substrate. A plurality of conductive layers in parallel arrangement is formed on the substrate and crosses the device isolation structures. A plurality of trench devices is formed between device isolation structures under the conductive layers. Each trench device includes a first conductive doping region at the bottom of the trench. The method further includes forming spacers on the sidewalls of the device isolation structures and the conductive layers. A dopant implant process is then performed by using the spacers as a mask to form a second conductive doping region between adjacent first conductive doping regions.

Abstract: A method for fabricating a wire with silicide is disclosed. First, a conductive layer is formed on a substrate. And, a hard mask layer is formed on the conductive layer. Then, the hard mask layer is used as a mask to remove a portion of the conductive layer. Afterwards, a spacer is formed on the sidewalls of the conductive layer and the hard mask layer. Afterwards, the hard mask layer is removed. Next, a silicide is formed on the conductive layer.

Abstract: A method for manufacturing a semiconductor device is disclosed suitable for a substrate having a first conducting structure and a first dielectric layer, wherein the dielectric layer covers the first conductive structure. The method includes the steps of forming a second conductive structure over the substrate adjacent to the first conductive structure. Then, the size of the second conductive structure is reduced so that a top surface of the second conductive structure is relatively lower than that of the first conductive structure. Thereafter, a second dielectric layer is formed over the substrate to cover the first and the second conductive structure. A via is formed in the second dielectric layer to expose the top surface of the first conductive structure. Finally, a via plug is formed in the via.

Abstract: A method for fabricating a semiconductor device is described. The method includes providing a substrate having a trench therein, and a trench device in the trench. The trench device includes two gate structures disposed on the sidewalls of the trench, a doped region in the substrate between the gate structures and an inter-gate dielectric layer disposed on the surface of the gate structures. A thermal treatment process in a nitrogen-containing ambient is performed to remove the native oxide layer formed on the surface of the doped region. Then, a conductive layer is formed to fill in the trench.

Abstract: A method for manufacturing an anti-punch through semiconductor device is described. The method is applied to a substrate having a plurality of device isolation structures in parallel arrangements and the upper surface of the device isolation structures is protruded from the surface of the substrate. A plurality of conductive layers in parallel arrangement is formed on the substrate and crosses the device isolation structures. A plurality of trench devices is formed between device isolation structures under the conductive layers. Each trench device includes a first conductive doping region at the bottom of the trench. The method further includes forming spacers on the sidewalls of the device isolation structures and the conductive layers. A dopant implant process is then performed by using the spacers as a mask to form a second conductive doping region between adjacent first conductive doping regions.

Abstract: A method of forming a floating gate of a memory cell is provided. A substrate having at least a trench is provided. Next, a tunnel oxide layer is formed on a surface of the trench. Next, a conductive layer is filled in the trench. Next, two-step etching process is carried out to form a first floating gate and a second floating gate having a top corner with sharp edge over the sidewalls of the trench.