Patents by Inventor Reynaldo Co

Reynaldo Co has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9082753
    Abstract: An electrically conductive lead is formed using a bonding tool. After bonding the wire to a metal surface and extending a length of the wire beyond the bonding tool, the wire is clamped. Movement of the bonding tool imparts a kink to the wire at a location where the wire is fully separated from any metal element other than the bonding tool. A forming element, e.g., an edge or a blade skirt provided at an exterior surface of the bonding tool can help kink the wire. Twisting the wire while tensioning the wire using the bonding tool can cause the wire to break and define an end. The lead then extends from the metal surface to the end, and may exhibits a sign of the torsional force applied thereto.
    Type: Grant
    Filed: June 6, 2014
    Date of Patent: July 14, 2015
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Reynaldo Co, Rizza Lee Saga Cizek, Wael Zohni
  • Patent number: 9041227
    Abstract: A microelectronic package includes a substrate having a first surface. A microelectronic element overlies the first surface. Electrically conductive elements are exposed at the first surface of the substrate, at least some of which are electrically connected to the microelectronic element. The package includes wire bonds having bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. The ends of the wire bonds are defined on tips of the wire bonds, and the wire bonds define respective first diameters between the bases and the tips thereof. The tips have at least one dimension that is smaller than the respective first diameters of the wire bonds. A dielectric encapsulation layer covers portions of the wire bonds, and unencapsulated portions of the wire bonds are defined by portions of the wire bonds, including the ends, are uncovered by the encapsulation layer.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: May 26, 2015
    Assignee: Invensas Corporation
    Inventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
  • Publication number: 20150129646
    Abstract: An electrically conductive lead is formed using a bonding tool. After bonding the wire to a metal surface and extending a length of the wire beyond the bonding tool, the wire is clamped. Movement of the bonding tool imparts a kink to the wire at a location where the wire is fully separated from any metal element other than the bonding tool. A forming element, e.g., an edge or a blade skirt provided at an exterior surface of the bonding tool can help kink the wire. Tensioning the wire using the bonding tool causes the wire to break and define an end. The lead then extends from the metal surface to the end.
    Type: Application
    Filed: November 12, 2013
    Publication date: May 14, 2015
    Applicant: Invensas Corporation
    Inventors: Belgacem Haba, Reynaldo Co, Rizza Lee Saga Cizek, Wael Zohni
  • Publication number: 20150129647
    Abstract: An electrically conductive lead is formed using a bonding tool. After bonding the wire to a metal surface and extending a length of the wire beyond the bonding tool, the wire is clamped. Movement of the bonding tool imparts a kink to the wire at a location where the wire is fully separated from any metal element other than the bonding tool. A forming element, e.g., an edge or a blade skirt provided at an exterior surface of the bonding tool can help kink the wire. Twisting the wire while tensioning the wire using the bonding tool can cause the wire to break and define an end. The lead then extends from the metal surface to the end, and may exhibits a sign of the torsional force applied thereto.
    Type: Application
    Filed: June 6, 2014
    Publication date: May 14, 2015
    Inventors: Belgacem Haba, Reynaldo Co, Rizza Lee Saga Cizek, Wael Zohni
  • Publication number: 20150034371
    Abstract: A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element.
    Type: Application
    Filed: October 17, 2014
    Publication date: February 5, 2015
    Applicant: INVENSAS CORPORATION
    Inventors: Belgacem Haba, Ilyas Mohammed, Terrence Caskey, Reynaldo Co, Ellis Chau
  • Publication number: 20150017765
    Abstract: A microelectronic assembly (10) includes a substrate (12) having a first and second opposed surfaces. A microelectronic element (22) overlies the first surface and first electrically conductive elements (28) can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements (28) are electrically connected to the microelectronic element (22). Wire bonds (32) have bases (34) joined to the conductive elements (28) and end surfaces (38) remote from the substrate and the bases, each wire bond defining an edge surface (37) extending between the base and the end surface. An encapsulation layer (42) can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds (32) are defined by at least portions of the end surfaces (38) of the wire bonds that are uncovered by the encapsulation layer (42).
    Type: Application
    Filed: February 14, 2013
    Publication date: January 15, 2015
    Applicant: INVENSAS CORPORATION
    Inventors: Reynaldo Co, Laura Mirkarimi
  • Patent number: 8884403
    Abstract: According to the invention, die shift is reduced or substantially eliminated, by cutting the wafer in two stages. In some embodiments a first wafer cutting procedure is carried out prior to thinning the wafer to the prescribed die thickness; and in other embodiments the wafer is thinned to the prescribed die thickness prior to carrying out a first wafer cutting procedure. The first wafer cutting procedure includes cutting along a first set of streets to a depth greater than the prescribed die thickness and optionally along a second set of streets to a depth less than the die thickness. The result of the first cutting procedure is an array of strips or blocks of die, each including a plurality of connected die, that are less subject to shift than are individual singulated die. In a second wafer cutting procedure the die are singulated by cutting through along the second set of streets.
    Type: Grant
    Filed: December 30, 2010
    Date of Patent: November 11, 2014
    Assignee: Iinvensas Corporation
    Inventors: Reynaldo Co, DeAnn Eileen Melcher, Weiping Pan, Grant Villavicencio
  • Patent number: 8878353
    Abstract: A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: November 4, 2014
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Terrence Caskey, Reynaldo Co, Ellis Chau
  • Patent number: 8836136
    Abstract: A microelectronic package can include wire bonds having bases bonded to respective conductive elements on a substrate and ends opposite the bases. A dielectric encapsulation layer extending from the substrate covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds which are uncovered by the encapsulation layer. Unencapsulated portions can be disposed at positions in a pattern having a minimum pitch which is greater than a first minimum pitch between bases of adjacent wire bonds.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: September 16, 2014
    Assignee: Invensas Corporation
    Inventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang, Zhijun Zhao
  • Patent number: 8772152
    Abstract: A microelectronic assembly includes a substrate having a first and second opposed surfaces. A microelectronic element overlies the first surface and first electrically conductive elements can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the substrate and the bases, each wire bond defining an edge surface extending between the base and the end surface. An encapsulation layer can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: July 8, 2014
    Assignee: Invensas Corporation
    Inventors: Reynaldo Co, Laura Mirkarimi
  • Publication number: 20140175671
    Abstract: A structure may include bond elements having bases joined to conductive elements at a first portion of a first surface and end surfaces remote from the substrate. A dielectric encapsulation element may overlie and extend from the first portion and fill spaces between the bond elements to separate the bond elements from one another. The encapsulation element has a third surface facing away from the first surface. Unencapsulated portions of the bond elements are defined by at least portions of the end surfaces uncovered by the encapsulation element at the third surface. The encapsulation element at least partially defines a second portion of the first surface that is other than the first portion and has an area sized to accommodate an entire area of a microelectronic element. Some conductive elements are at the second portion and configured for connection with such microelectronic element.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Applicant: INVENSAS CORPORATION
    Inventors: Belgacem Haba, Ilyas Mohammed, Terrence Caskey, Reynaldo Co, Ellis Chau
  • Patent number: 8680687
    Abstract: A die (or of a stack of die) is mounted over and elevated above a support, and is electrically connected to circuitry in the support. Pillars of electrically conductive material are formed on a set of bond pads at a mount side of the support, and the elevated die (or at least one die in the elevated stack of die) is electrically connected to the support, by traces of an electrically conductive material contacting interconnect pads on the die to the pillars, and through the pillars to the support. Also, tiered offset stacked die assemblies in a zig-zag configuration, in which the interconnect edges of a first (lower) tier face in a first direction, and the interconnect edges of a second (upper) tier, stacked over the first tier, face in a second direction, different from the first direction, are electrically connected to a support.
    Type: Grant
    Filed: June 23, 2010
    Date of Patent: March 25, 2014
    Assignee: Invensas Corporation
    Inventors: Reynaldo Co, Grant Villavicencio, Jeffrey S. Leal, Simon J. S. McElrea
  • Publication number: 20140036454
    Abstract: A method for making an interposer includes forming a plurality of wire bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is formed contacting an edge surface of the wire bonds which separates adjacent wire bonds from one another. Further processing comprises removing at least portions of the first element, wherein the interposer has first and second opposite sides separated from one another by at least the encapsulation, and the interposer having first contacts and second contacts at the first and second opposite sides, respectively, for electrical connection with first and second components, respectively, the first contacts being electrically connected with the second contacts through the wire bonds.
    Type: Application
    Filed: March 12, 2013
    Publication date: February 6, 2014
    Applicant: INVENSAS CORPORATION
    Inventors: Terrence Caskey, Ilyas Mohammed, Cyprian Emeka Uzoh, Charles G. Woychik, Michael Newman, Pezhman Monadgemi, Reynaldo Co, Ellis Chau, Belgacem Haba
  • Publication number: 20130328219
    Abstract: A structure includes a substrate having a first region and a second region, the substrate also having a first surface and a second surface. Electrically conductive elements are exposed at the first surface within the second region. Wire bonds have bases bonded to respective ones of the conductive elements and ends remote from the substrate and remote from the bases. At least one of the wire bonds has a shape such that the wire bond defines an axis between the free end and the base thereof and such that the wire bond defines a plane. A bent portion of the at least one wire bond extends away from the axis within the plane. A dielectric encapsulation layer covers portions of the wire bonds such that unencapsulated portions, including the ends, of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer.
    Type: Application
    Filed: August 14, 2013
    Publication date: December 12, 2013
    Applicant: INVENSAS CORPORATION
    Inventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
  • Publication number: 20130095610
    Abstract: A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 92° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds.
    Type: Application
    Filed: February 24, 2012
    Publication date: April 18, 2013
    Applicant: INVENSAS CORPORATION
    Inventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
  • Publication number: 20130093087
    Abstract: A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 90° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds.
    Type: Application
    Filed: February 24, 2012
    Publication date: April 18, 2013
    Applicant: INVENSAS CORPORATION
    Inventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
  • Publication number: 20130093088
    Abstract: A microelectronic package can include wire bonds having bases bonded to respective conductive elements on a substrate and ends opposite the bases. A dielectric encapsulation layer extending from the substrate covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds which are uncovered by the encapsulation layer. Unencapsulated portions can be disposed at positions in a pattern having a minimum pitch which is greater than a first minimum pitch between bases of adjacent wire bonds.
    Type: Application
    Filed: February 24, 2012
    Publication date: April 18, 2013
    Applicant: INVENSAS CORPORATION
    Inventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang, Zhijun Zhao
  • Patent number: 8404520
    Abstract: A microelectronic package can include wire bonds having bases bonded to respective ones of conductive elements exposed at a surface of a substrate. The wire bonds may have exterior edge surfaces disposed at an angle between 25° and 92° relative to the bases, and ends remote, e.g., opposite, from the bases, and remote from the ends which are connected to the bases. A dielectric encapsulation layer extends from the substrate and covers portions of the wire bonds such that covered portions of the wire bonds are separated from one another by the encapsulation layer, wherein unencapsulated portions of the wire bonds are defined by portions of the wire bonds that are uncovered by the encapsulation layer, the unencapsulated portions including the ends of the wire bonds.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: March 26, 2013
    Assignee: Invensas Corporation
    Inventors: Ellis Chau, Reynaldo Co, Roseann Alatorre, Philip Damberg, Wei-Shun Wang, Se Young Yang
  • Patent number: 8372741
    Abstract: A microelectronic assembly includes a substrate having a first and second opposed surfaces. A microelectronic element overlies the first surface and first electrically conductive elements can be exposed at at least one of the first surface or second surfaces. Some of the first conductive elements are electrically connected to the microelectronic element. Wire bonds have bases joined to the conductive elements and end surfaces remote from the substrate and the bases, each wire bond defining an edge surface extending between the base and the end surface. An encapsulation layer can extend from the first surface and fill spaces between the wire bonds, such that the wire bonds can be separated by the encapsulation layer. Unencapsulated portions of the wire bonds are defined by at least portions of the end surfaces of the wire bonds that are uncovered by the encapsulation layer.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: February 12, 2013
    Assignee: Invensas Corporation
    Inventors: Reynaldo Co, Laura Mirkarimi
  • Patent number: 8324081
    Abstract: An electrically insulative conformal coating is applied at least to the active (front) side and one or more sidewalls of the die during wafer processing. Also, a die has an electrically insulative conformal coating applied to at least the active (front) side and sidewalls. Also, assemblies include a stack of such die, electrically interconnected die-to-die; and assemblies include such a die or a stack of such die, electrically interconnected to underlying circuitry (for example in a substrate or a circuit board).
    Type: Grant
    Filed: March 4, 2011
    Date of Patent: December 4, 2012
    Inventors: Simon J. S. McElrea, Terrence Caskey, Scott McGrath, DeAnn Eileen Melcher, Reynaldo Co, Lawrence Douglas Andrews, Jr., Weiping Pan, Grant Villavicencio, Yong Du, Scott Jay Crane, Zongrong Liu