Patents by Inventor Reynante Tamunan Alvarado
Reynante Tamunan Alvarado has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11545411Abstract: A package that includes a substrate, an integrated device, a plurality of first wire bonds, at least one second wire bond, and an encapsulation layer. The integrated device is coupled to the substrate. The plurality of first wire bonds is coupled to the integrated device and the substrate. The plurality of first wire bonds is configured to provide at least one electrical path between the integrated device and the substrate. The at least one second wire bond is coupled to the integrated device. The at least one second wire bond is configured to be free of an electrical connection with a circuit of the integrated device. The encapsulation layer is located over the substrate and the integrated device. The encapsulation layer encapsulates the integrated device, the plurality of first wire bonds and the at least one second wire bond.Type: GrantFiled: July 28, 2020Date of Patent: January 3, 2023Assignee: QUALCOMM INCORPORATEDInventors: Wen Yin, Yonghao An, Reynante Tamunan Alvarado
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Publication number: 20220037224Abstract: A package that includes a substrate, an integrated device, a plurality of first wire bonds, at least one second wire bond, and an encapsulation layer. The integrated device is coupled to the substrate. The plurality of first wire bonds is coupled to the integrated device and the substrate. The plurality of first wire bonds is configured to provide at least one electrical path between the integrated device and the substrate. The at least one second wire bond is coupled to the integrated device. The at least one second wire bond is configured to be free of an electrical connection with a circuit of the integrated device. The encapsulation layer is located over the substrate and the integrated device. The encapsulation layer encapsulates the integrated device, the plurality of first wire bonds and the at least one second wire bond.Type: ApplicationFiled: July 28, 2020Publication date: February 3, 2022Inventors: Wen YIN, Yonghao AN, Reynante Tamunan ALVARADO
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Patent number: 10163687Abstract: A package may include a die proximate to a structure having a substrate with interconnects and a first component coupled to the interconnects. The die may be face up or face down. The package may include a first redistribution layer coupling the die to the interconnects of the structure and a mold compound covering the die and maybe the structure.Type: GrantFiled: September 22, 2015Date of Patent: December 25, 2018Assignee: QUALCOMM IncorporatedInventors: David Fraser Rae, Lizabeth Ann Keser, Reynante Tamunan Alvarado
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Patent number: 10141202Abstract: Some implementations provide a semiconductor device that includes a substrate, several metal and dielectric layers coupled to the substrate, and a pad coupled to one of the several metal layers. The semiconductor device also includes a first metal layer coupled to the pad and an under bump metallization layer coupled to the first metal redistribution layer. The semiconductor device further includes a mold layer covering a first surface of the semiconductor device and at least a side portion of the semiconductor device. In some implementations, the mold layer is an epoxy layer. In some implementations, the first surface of the semiconductor device is the top side of the semiconductor device. In some implementations, the mold layer covers the at least side portion of the semiconductor device such that a side portion of at least one of the several metal layers and dielectric layers is covered with the mold layer.Type: GrantFiled: May 20, 2013Date of Patent: November 27, 2018Assignee: QUALCOMM IncorporatedInventors: Reynante Tamunan Alvarado, Lizabeth Ann Keser, Jianwen Xu
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Patent number: 9985010Abstract: An integrated package may be manufactured in a die face up orientation with a component proximate to the attached die by creating a cavity in the mold compound during fabrication. The cavity is created with an adhesive layer on the bottom to hold a component such that the top surface of the component is co-planar with the top surface of the attached die. This may allow backside grinding to take place that will not damage the component because the top surface alignment between the attached die and the component prevents the depth of the cavity from extending into the portion of the package that is ground away.Type: GrantFiled: September 20, 2015Date of Patent: May 29, 2018Assignee: QUALCOMM IncorporatedInventors: David Fraser Rae, Lizabeth Ann Keser, Reynante Tamunan Alvarado
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Publication number: 20170373032Abstract: Disclosed is a fan-out wafer level packaging (FOWLP) apparatus includes a semiconductor die having at least one input/output (I/O) connection, a first plurality of package balls having a first package ball layout, a first conductive layer forming a first redistribution layer (RDL) and configured to electrically couple to the first plurality of package balls, and a second conductive layer forming a second RDL and including at least one conductive pillar configured to electrically couple the at least one I/O connection of the semiconductor die to the first conductive layer, wherein the second conductive layer enables the semiconductor die to be electrically coupled to a second plurality of package balls having a second package ball layout without a change in position of the at least one I/O connection of the semiconductor die.Type: ApplicationFiled: June 24, 2016Publication date: December 28, 2017Inventors: Jihoon OH, Ruey Kae ZANG, Lizabeth Ann KESER, Reynante Tamunan ALVARADO, Haiyong XU, Yue LI, Steve BEZUK
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Patent number: 9806052Abstract: A semiconductor package interconnect system may include a conductive pillar having a core, a first layer surrounding the core, and a second layer surrounding the first layer. The core may be composed of a drawn copper wire, the first layer may be composed of nickel, and the second layer may be composed of a solder. A method for manufacturing a semiconductor package with such a conductive pillar may include placing a plurality of conductive pillars on a substrate using a stencil process.Type: GrantFiled: September 15, 2015Date of Patent: October 31, 2017Assignee: QUALCOMM IncorporatedInventors: Lizabeth Ann Keser, Reynante Tamunan Alvarado
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Patent number: 9806048Abstract: A proposed device may reduce or eliminate a step between a die and a mold compound. Bottom and top surfaces of the die may respectively be the active and non-active sides of the die. The mold compound maybe above the top surface of the die in a fan-in area corresponding to a lateral width of the die and may also be in a fan-out area corresponding to an area that extends laterally away from a side surface of the die. The mold compound in the fan-in area need not be coplanar with the mold compound in at least a portion of the fan-out area. The device may also include a redistribution layer below the bottom surface of the die and below the mold compound, and may further include an interconnect below the redistribution layer and electrically coupled to the die through the redistribution layer. A portion of the redistribution layer may be in the fan-out area.Type: GrantFiled: March 16, 2016Date of Patent: October 31, 2017Assignee: QUALCOMM IncorporatedInventors: Lizabeth Ann Keser, David Fraser Rae, Reynante Tamunan Alvarado
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Publication number: 20170271289Abstract: A proposed device may reduce or eliminate a step between a die and a mold compound. Bottom and top surfaces of the die may respectively be the active and non-active sides of the die. The mold compound maybe above the top surface of the die in a fan-in area corresponding to a lateral width of the die and may also be in a fan-out area corresponding to an area that extends laterally away from a side surface of the die. The mold compound in the fan-in area need not be coplanar with the mold compound in at least a portion of the fan-out area. The device may also include a redistribution layer below the bottom surface of the die and below the mold compound, and may further include an interconnect below the redistribution layer and electrically coupled to the die through the redistribution layer. A portion of the redistribution layer may be in the fan-out area.Type: ApplicationFiled: March 16, 2016Publication date: September 21, 2017Inventors: Lizabeth Ann KESER, David Fraser RAE, Reynante Tamunan ALVARADO
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Publication number: 20170077053Abstract: A semiconductor package interconnect system may include a conductive pillar having a core, a first layer surrounding the core, and a second layer surrounding the first layer. The core may be composed of a drawn copper wire, the first layer may be composed of nickel, and the second layer may be composed of a solder. A method for manufacturing a semiconductor package with such a conductive pillar may include placing a plurality of conductive pillars on a substrate using a stencil process.Type: ApplicationFiled: September 15, 2015Publication date: March 16, 2017Inventors: Lizabeth Ann KESER, Reynante Tamunan ALVARADO
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Publication number: 20160343646Abstract: A package (e.g., wafer level package) that includes a die, a redistribution portion coupled to the die, a first high aspect ratio (HAR) interconnect coupled to the redistribution portion of the package, where the first high aspect ratio (HAR) interconnect comprises a width to height ratio of about at least 1:2, and a first solder interconnect coupled to the first high aspect ratio (HAR) interconnect and the redistribution portion. In some implementations, the first high aspect ratio (HAR) interconnect is a composite interconnect that includes a first conductive core and a first conductive layer that at least partially encapsulates the first conductive core. In some implementations, the first conductive layer is a diffusion barrier.Type: ApplicationFiled: August 26, 2015Publication date: November 24, 2016Inventors: Reynante Tamunan Alvarado, Lizabeth Ann Keser, Tong Cui
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Publication number: 20160343635Abstract: An integrated package may be manufactured in a die face up orientation with a component proximate to the attached die by creating a cavity in the mold compound during fabrication. The cavity is created with an adhesive layer on the bottom to hold a component such that the top surface of the component is co-planar with the top surface of the attached die. This may allow backside grinding to take place that will not damage the component because the top surface alignment between the attached die and the component prevents the depth of the cavity from extending into the portion of the package that is ground away.Type: ApplicationFiled: September 20, 2015Publication date: November 24, 2016Inventors: David Fraser RAE, Lizabeth Ann KESER, Reynante Tamunan ALVARADO
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Publication number: 20160343651Abstract: A package may include a die proximate to a structure having a substrate with interconnects and a first component coupled to the interconnects. The die may be face up or face down. The package may include a first redistribution layer coupling the die to the interconnects of the structure and a mold compound covering the die and maybe the structure.Type: ApplicationFiled: September 22, 2015Publication date: November 24, 2016Inventors: David Fraser RAE, Lizabeth Ann KESER, Reynante Tamunan ALVARADO
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Patent number: 9379065Abstract: Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the several metal layers, a first metal redistribution layer coupled to the pad, an under bump metallization (UBM) layer coupled to the first metal redistribution layer. The semiconductor device includes several crack stopping structures configured to surround a bump area of the semiconductor device and a pad area of the semiconductor device. The bump area includes the UBM layer. The pad area includes the pad. In some implementations, at least one crack stopping structure includes a first metal layer and a first via. In some implementations, at least one crack stopping structure further includes a second metal layer, a second via, and a third metal layer. In some implementations, at least one crack stopping structure is an inverted pyramid crack stopping structure.Type: GrantFiled: August 16, 2013Date of Patent: June 28, 2016Assignee: QUALCOMM IncorporatedInventors: Lizabeth Ann Keser, Zhongping Bao, Reynante Tamunan Alvarado
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Patent number: 9209110Abstract: Some novel features pertain to an integrated device that includes a substrate, a first die coupled to the substrate, a first encapsulation layer coupled to the substrate and the first die, and a second encapsulation layer in the first encapsulation layer. The second encapsulation layer includes a set of wires configured to operate as vias. In some implementations, the integrated device includes a set of vias in the first encapsulation layer. In some implementations, the integrated device further includes a second die coupled to the substrate. In some implementations, the second encapsulation layer is positioned between the first die and the second die. In some implementations, the integrated device further includes a cavity in the first encapsulation layer, where the second encapsulation layer is positioned in the cavity. In some implementations, the cavity has a wall that is non-vertical. In some implementations, at least one of the wires is non-vertical.Type: GrantFiled: May 7, 2014Date of Patent: December 8, 2015Assignee: QUALCOMM IncorporatedInventors: Reynante Tamunan Alvarado, Lizabeth Ann Keser, Steve Joseph Bezuk
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Publication number: 20150325496Abstract: Some novel features pertain to an integrated device that includes a substrate, a first die coupled to the substrate, a first encapsulation layer coupled to the substrate and the first die, and a second encapsulation layer in the first encapsulation layer. The second encapsulation layer includes a set of wires configured to operate as vias. In some implementations, the integrated device includes a set of vias in the first encapsulation layer. In some implementations, the integrated device further includes a second die coupled to the substrate. In some implementations, the second encapsulation layer is positioned between the first die and the second die. In some implementations, the integrated device further includes a cavity in the first encapsulation layer, where the second encapsulation layer is positioned in the cavity. In some implementations, the cavity has a wall that is non-vertical. In some implementations, at least one of the wires is non-vertical.Type: ApplicationFiled: May 7, 2014Publication date: November 12, 2015Applicant: QUALCOMM IncorporatedInventors: Reynante Tamunan Alvarado, Lizabeth Ann Keser, Steve Joseph Bezuk
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Patent number: 9171782Abstract: Some implementations provide a semiconductor device (e.g., die) that includes a substrate, several metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the plurality of metal layers, a first metal redistribution layer coupled to the pad, and a second metal redistribution layer coupled to the first metal redistribution layer. The second metal redistribution layer includes a cobalt tungsten phosphorous material. In some implementations, the first metal redistribution layer is a copper layer. In some implementations, the semiconductor device further includes a first underbump metallization (UBM) layer and a second underbump metallization (UBM) layer.Type: GrantFiled: August 6, 2013Date of Patent: October 27, 2015Assignee: QUALCOMM IncorporatedInventors: Christine Sung-An Hau-Riege, You-Wen Yau, Kevin Patrick Caffey, Lizabeth Ann Keser, Gene Hyde McAllister, Reynante Tamunan Alvarado, Steve Joseph Bezuk, Damion Bryan Gastelum
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Publication number: 20150228594Abstract: A semiconductor device is provided that has a redistribution layer with reduced resistance. The semiconductor device comprises a plurality of bonding pads on a substrate, a redistribution layer coupled to the bonding pads through a plurality of vias, a dielectric layer over the redistribution layer, that includes an opening that exposes a portion of the redistribution layer. The bonding pads are at least partially under the opening.Type: ApplicationFiled: March 21, 2014Publication date: August 13, 2015Applicant: QUALCOMM INCORPORATEDInventors: Reynante Tamunan Alvarado, Ruey Kae Zang, Lizabeth Ann Keser
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Publication number: 20150048517Abstract: Some implementations provide a semiconductor device (e.g., die, wafer) that includes a substrate, metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the several metal layers, a first metal redistribution layer coupled to the pad, an under bump metallization (UBM) layer coupled to the first metal redistribution layer. The semiconductor device includes several crack stopping structures configured to surround a bump area of the semiconductor device and a pad area of the semiconductor device. The bump area includes the UBM layer. The pad area includes the pad. In some implementations, at least one crack stopping structure includes a first metal layer and a first via. In some implementations, at least one crack stopping structure further includes a second metal layer, a second via, and a third metal layer. In some implementations, at least one crack stopping structure is an inverted pyramid crack stopping structure.Type: ApplicationFiled: August 16, 2013Publication date: February 19, 2015Applicant: QUALCOMM IncorporatedInventors: Lizabeth Ann Keser, Zhongping Bao, Reynante Tamunan Alvarado
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Publication number: 20150041982Abstract: Some implementations provide a semiconductor device (e.g., die) that includes a substrate, several metal layers and dielectric layers coupled to the substrate, a pad coupled to one of the plurality of metal layers, a first metal redistribution layer coupled to the pad, and a second metal redistribution layer coupled to the first metal redistribution layer. The second metal redistribution layer includes a cobalt tungsten phosphorous material. In some implementations, the first metal redistribution layer is a copper layer. In some implementations, the semiconductor device further includes a first underbump metallization (UBM) layer and a second underbump metallization (UBM) layer.Type: ApplicationFiled: August 6, 2013Publication date: February 12, 2015Applicant: QUALCOMM IncorporatedInventors: Christine Sung-An Hau-Riege, You-Wen Yau, Kevin Patrick Caffey, Lizabeth Ann Keser, Gene H. McAllister, Reynante Tamunan Alvarado, Steve J. Bezuk, Damion Bryan Gastelum