Abstract: An apparatus comprising: a drive carrier assembly (DCA) including; an energy storage device having at least a portion thereof encased by a housing; and a printed circuit assembly to detect a power failure of a host computing device, wherein the printed circuit assembly has a first portion coupled to the energy storage device and a second portion coupled to a backplane of the host computing device.

Abstract: In some examples, a memory module includes an error status indicator, an error address register, and error tracking circuitry. The error tracking circuitry may detect that memory data stored at a memory address for the memory module includes an error. In response, and without overwriting the memory data stored at the memory address, the error tracking circuitry may set the error status indicator and store the memory address in the error address register.

Abstract: An example apparatus comprises a drive carrier assembly which may include a memory device, and an energy storage device having at least a portion thereof encased in a housing. In some examples, the apparatus may include a printed circuit assembly to detect a power failure of a host computing device. The printed circuit assembly, may have a first portion coupled to the energy storage device and a second portion coupled to a backplane of the host computing device.

Abstract: One example includes a system. The system includes an error injection system. The error injection system includes an error injector to store a programmable control structure to define a memory error. The error injector being further used to inject the memory error into a respective one of a plurality of memory storage elements associated with a memory system at a predetermined address via an address controller and to determine if the memory error at the predetermined address associated with the respective one of the plurality of memory storage elements is corrected via error-correcting code (ECC) memory associated with the memory system.

Abstract: An apparatus comprising: a drive carrier assembly (DCA) including; an energy storage device having at least a portion thereof encased by a housing; and a printed circuit assembly to detect a power failure of a host computing device, wherein the printed circuit assembly has a first portion coupled to the energy storage device and a second portion coupled to a backplane of the host computing device

Abstract: In one implementation, a memory module with on-die error correction code (ECC) with scrub operation capabilities and a programmable patrol scrub period is coupled to a memory controller that causes error correction operations to perform based on a power status of an energy storage device.

Abstract: A volatile memory device includes a memory array of volatile charge storage cells, a counter to track a time since the volatile memory device has received a read/write command and a control element to automatically change the volatile memory device to a lower power state based on the time tracked by the counter.

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. A sufficient number of stitching capacitors are to couple the first power plane to a second power plane.

Abstract: An example apparatus comprises a drive carrier assembly which may include a memory device, and an energy storage device having at least a portion thereof encased in a housing. In some examples, the apparatus may include a printed circuit assembly to detect a power failure of a host computing device. The printed circuit assembly, may have a first portion coupled to the energy storage device and a second portion coupled to a backplane of the host computing device.

Abstract: An example system includes a memory controller; a memory bus coupled to the memory controller; and a dual inline memory module (DIMM) coupled to the memory controller through the memory bus. The DIMM includes a dynamic random access memory (DRAM) portion; a storage portion; and a gate array portion coupled to the memory bus to detect memory access signals and to store information related to the memory access signals on the storage portion.

Abstract: One example includes a system. The system includes an error injection system. The error injection system includes an error injector to store a programmable control structure to define a memory error. The error injector being further used to inject the memory error into a respective one of a plurality of memory storage elements associated with a memory system at a predetermined address via an address controller and to determine if the memory error at the predetermined address associated with the respective one of the plurality of memory storage elements is corrected via error-correcting code (ECC) memory associated with the memory system.

Abstract: A volatile memory device includes a memory array of volatile charge storage cells, a counter to track a time since the volatile memory device has received a read/write command and a control element to automatically change the volatile memory device to a lower power state based on the time tracked by the counter.

Abstract: A memory device includes a memory storage media to store data for the memory device. A memory manager initiates an autonomous precharge of a buffered page into the memory storage media in the absence of detecting a command at an input of the memory device for a period of time that exceeds a threshold.

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. A sufficient number of stitching capacitors are to couple the first power plane to a second power plane.

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. At least one stitching capacitor is to couple the first power plane to a second power plane.

Abstract: In some examples, a memory module includes an error status indicator, an error address register, and error tracking circuitry. The error tracking circuitry may detect that memory data stored at a memory address for the memory module includes an error. In response, and without overwriting the memory data stored at the memory address, the error tracking circuitry may set the error status indicator and store the memory address in the error address register.

Abstract: An example device in accordance with an aspect of the present disclosure includes a memory module having a voltage regulator module (VRM) to receive input power and deliver output power to components of the memory module at a first power plane. At least one stitching capacitor is to couple the first power plane to a second power plane.

Abstract: An example system includes a memory controller; a memory bus coupled to the memory controller; and a dual inline memory module (DIMM) coupled to the memory controller through the memory bus. The DIMM includes a dynamic random access memory (DRAM) portion; a storage portion; and a gate array portion coupled to the memory bus to detect memory access signals and to store information related to the memory access signals on the storage portion.

Abstract: Techniques are described for assigning an application thread to a cache. A newly created application thread may be assigned to a plurality of caches. The cache assignment that optimizes performance may be determined. The newly created application thread may be associated with the determined cache.

Abstract: A technique includes during in-service use of a memory package in a computer system, using a first interface to access a defective address memory of the memory package. The defective address memory is accessible by a manufacturer of the memory package prior to the in-service use using a second interface of the memory package other than the first interface. In connection with the in-service use of the memory package, the memory package is repair, a repair that includes storing a defective address in the defective address memory to change an address mapping for at least one cell of the storage array.