Abstract: An apparatus includes a memory module, and the memory module includes a package. The package contains memory dies, and the memory dies share a chip select line.

Abstract: A system includes a hybrid memory module. The hybrid memory module includes volatile memory and non-volatile memory. The system further includes a processor coupled to the hybrid memory module. The processor prevents the hybrid memory module from being mapped during a memory initialization routine by misrepresenting a status of the hybrid memory module.

Abstract: Techniques are described for assigning an application thread to a cache. A newly created application thread may be assigned to a plurality of caches. The cache assignment that optimizes performance may be determined. The newly created application thread may be associated with the determined cache.

Abstract: Embodiments of the present invention are directed to a memory subsystem comprising a memory controller, multiple memory modules interconnected with the memory controller by one or more communications media, each memory module comprising a substrate to which multiple memory chips are mounted and electronically connected to the communications media, and a power-supply signal routed to two or more voltage regulators within the memory subsystem from a system power supply, the voltage regulators outputting two or more internal power signals, each power signal providing a different, regulated voltage, which are routed to each of the memory chips. Another embodiment of the present invention is directed to a memory module comprising a substrate to which multiple memory chips are mounted and two or more voltage regulators mounted to, or fabricated within, the substrate.

Abstract: A computer power management system (10) can include power demand logic (20) of a computer component (12) that can generate a power demand signal corresponding to a predicted power demand determined for the computer component (12). A voltage regulator down (VRD) system (14) includes at least one power phase (18). The VRD system (14) can selectively adjust an input power to the computer component (12) based on power efficiency in response to the power demand signal.

Abstract: Embodiments of the present invention are directed to a memory subsystem comprising a memory controller, multiple memory modules interconnected with the memory controller by one or more communications media, each memory module comprising a substrate to which multiple memory chips are mounted and electronically connected to the communications media, and a power-supply signal routed to two or more voltage regulators within the memory subsystem from a system power supply, the voltage regulators outputting two or more internal power signals, each power signal providing a different, regulated voltage, which are routed to each of the memory chips. Another embodiment of the present invention is directed to a memory module comprising a substrate to which multiple memory chips are mounted and two or more voltage regulators mounted to, or fabricated within, the substrate.

Abstract: A voltage regulator is provided that includes current sense circuitry configured to detect an amount of current provided to a load, a voltage controlled oscillator configured to output a clock signal with a constant duty cycle at a frequency that varies in dependence on the amount of current detected by current sense circuitry, and regulator circuitry configured to provide a regulated voltage to the load using the clock signal.

Abstract: A method for phase shedding is disclosed. The method comprises the following steps. At step one power is supplied to a memory sub-system with a multi-phase regulator wherein a maximum number of phases in the multi-phase regulator are enabled. At step two the memory configuration of the memory sub-system is determined. At step three at least one of the phases of the multi-phase regulator is disabled when the memory configuration meets a predetermined criteria.

Abstract: In at least some embodiments, a system comprises a processor and a memory coupled to the processor. The memory stores processor performance utility instructions and performance adjustment instructions. When executed, the processor performance utility instructions are configured to cause activities of the processor to be counted and to cause a processor utilization value to be determined based on the counts. When executed, the performance adjustment instructions are configured to adjust the processor utilization value based on a comparison of the processor's current operating frequency and maximum operating frequency.

Abstract: A method includes querying a memory to determine what type of voltage the memory requires and applying the proper operating voltage to the memory based on the query. An apparatus that supports different memory types is also disclosed.

Abstract: A computer system determines whether a voltage signal that powers a slot circuitry and a card in one of two modes has been properly generated. If so, then the slot circuitry and the card are initialized in the one mode. Otherwise, the slot circuitry and the card are initialized in the other of the two modes.

Abstract: A first signal passes through a first layer of a circuit apparatus at a first propagation speed, and a second signal passes through a second layer of the circuit apparatus at a second propagation speed different from the first propagation speed.

Abstract: The cage-supported hard disk drives in a computer server system are coupled to connectors on the cage back plane circuit boards and are controlled by a pair of array controller cards which are hot-plug connected in a redundant manner on the system I/O board using a pair of connectors mounted on the I/O board, each connector having first and second sets of electrical contacts thereon. Connector edge portions of the array controller cards are plugged into the I/O board connectors and have first and second sets of electrical contacts that engage the corresponding first and second sets of electrical contacts on their associated I/O board connectors.