Patents by Inventor Rhys S. A. Philbrick

Rhys S. A. Philbrick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150067358
    Abstract: A system and method capable of injection locking the phases of a peak-valley multiphase regulator includes comparing an output voltage error signal with a ramp control signal and providing a corresponding slope reset signal, using transitions of the slope reset signal to develop a equally spaced high side ramp signals and equally spaced low side ramp signals, and injecting a corresponding one of the high side signals and a corresponding one of the low side ramp signals into each of the phases which correspondingly develop equally spaced pulse control signals for multiphase operation. Such injection locking allows the additional phases to operate out of phase with the first phase and allows operation at high duty cycles.
    Type: Application
    Filed: December 6, 2013
    Publication date: March 5, 2015
    Applicant: INTERSIL AMERICAS LLC
    Inventors: Rhys S.A. Philbrick, Emil Chen, Ruchi J. Parikh
  • Patent number: 8901910
    Abstract: A predictive current feedback system for a switched mode regulator including a sample and hold network for sampling voltage across a lower switch of the regulator and for providing a hold signal indicative thereof, and a predictive current feedback network which adds an offset adjustment to the hold signal based on a duration of a pulse width of a pulse control signal developed by the regulator. Sampling may be done while the lower switch is on for providing a hold value indicative of inductor current while the pulse control signal is low. The offset adjustment may be added to the hold signal in response to a transient event when the pulse signal is high. The offset may be incremental values after each of incremental time periods after a nominal time period, or may be a time-varying value. Adjustment may be made while the pulse signal is low as well.
    Type: Grant
    Filed: June 25, 2012
    Date of Patent: December 2, 2014
    Assignee: Intersil Americas LLC
    Inventors: Steven P. Laur, M. Jason Houston, Rhys S. A. Philbrick, Thomas A. Jochum
  • Patent number: 8860394
    Abstract: A dynamic voltage response network for a switching regulator with droop control providing a droop control signal includes a voltage identification setting network, a pass and hold system, and a reset network. The voltage identification setting network initiates a hold condition and adjusts an output voltage reference in response to a change in a voltage identification input. The pass and hold system passes the droop control signal during a pass condition and holds the droop control signal during the hold condition. The reset network resets the pass and hold system to the pass condition in response to a reset signal. The reset signal may be provided in response to a variety of conditions, such as load transients, proximity between the developed droop control signal and the held droop control signal, timeout after the output voltage reference is adjusted, among other reset conditions.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: October 14, 2014
    Assignee: Intersil Americas LLC
    Inventors: M. Jason Houston, Steven P. Laur, Rhys S. A. Philbrick
  • Patent number: 8786377
    Abstract: A variable frequency modulator including a compensation network, first and second pulse control networks and a linearity controller. The compensation network is configured to provide a compensation signal indicative of an output load condition. The first pulse control network is configured to initiate pulses on a pulse control signal and to adjust operating frequency based on changes of the compensation signal. The second pulse control network is configured to terminate the pulses on the pulse control signal based on a predetermined timing parameter. The linearity controller is configured to adjust timing of terminating the pulses based on a predetermined steady state operating frequency and an actual operating frequency to maintain modulator gain at a constant level.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: July 22, 2014
    Assignee: Intersil Americas LLC
    Inventors: M. Jason Houston, Steven P. Laur, Rhys S. A. Philbrick
  • Patent number: 8629662
    Abstract: A phase current sharing network that adjusts operation of a current mode multiphase switching regulator in which the phase current sharing network includes multiple synthetic ripple networks and a current share network. The regulator develops phase currents including ripple currents through corresponding phase inductors as controlled by corresponding pulse control signals. Each synthetic ripple networks develops a corresponding ripple voltage that simulates a corresponding phase ripple current and uses the ripple voltages to develop the pulse control signals. The current share network adjusts each ripple voltage by a combined adjustment value. The combined adjustment value is a combination of phase adjustment values in which each phase adjustment value is based on a difference between a corresponding one of ripple voltage and a reference voltage. Transconductance amplifiers may be used to convert the voltage differences to current adjust values applied to the ripple capacitors developing the ripple voltages.
    Type: Grant
    Filed: February 20, 2013
    Date of Patent: January 14, 2014
    Assignee: Intersil Americas LLC
    Inventors: Steven P. Laur, Rhys S. A. Philbrick
  • Publication number: 20140002047
    Abstract: A dynamic voltage response network for a switching regulator with droop control providing a droop control signal includes a voltage identification setting network, a pass and hold system, and a reset network. The voltage identification setting network initiates a hold condition and adjusts an output voltage reference in response to a change in a voltage identification input. The pass and hold system passes the droop control signal during a pass condition and holds the droop control signal during the hold condition. The reset network resets the pass and hold system to the pass condition in response to a reset signal. The reset signal may be provided in response to a variety of conditions, such as load transients, proximity between the developed droop control signal and the held droop control signal, timeout after the output voltage reference is adjusted, among other reset conditions.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Applicant: INTERSIL AMERICAS LLC
    Inventors: M. Jason Houston, Steven P. Laur, Rhys S.A. Philbrick
  • Publication number: 20130300388
    Abstract: A predictive current feedback system for a switched mode regulator including a sample and hold network for sampling voltage across a lower switch of the regulator and for providing a hold signal indicative thereof, and a predictive current feedback network which adds an offset adjustment to the hold signal based on a duration of a pulse width of a pulse control signal developed by the regulator. Sampling may be done while the lower switch is on for providing a hold value indicative of inductor current while the pulse control signal is low. The offset adjustment may be added to the hold signal in response to a transient event when the pulse signal is high. The offset may be incremental values after each of incremental time periods after a nominal time period, or may be a time-varying value. Adjustment may be made while the pulse signal is low as well.
    Type: Application
    Filed: June 25, 2012
    Publication date: November 14, 2013
    Applicant: INTERSIL AMERICAS LLC
    Inventors: Steven P. Laur, M. Jason Houston, Rhys S.A. Philbrick, Thomas A. Jochum
  • Publication number: 20130300392
    Abstract: A regulator system with dynamic droop including a regulator control network which is adapted to control regulation of an output voltage to a reference level, a DC droop network which provides a droop signal to modify the reference level based on output load according to a predetermined DC load line, and a dynamic droop network which adjusts the droop signal to delay recovery to the predetermined DC load line within an AC load line tolerance in response to a load transient. A transient reduction network may be included to reduce transient overshoot for load insertion or release depending upon duty cycle type. The dynamic droop network adjusts the droop signal to optimize utilization of an AC delay parameter while transitioning between an AC offset voltage allowance and the predetermined DC load line.
    Type: Application
    Filed: June 28, 2012
    Publication date: November 14, 2013
    Applicant: INTERSIL AMERICAS LLC
    Inventors: Steven P. Laur, M. Jason Houston, Rhys S.A. Philbrick, Thomas A. Jochum
  • Publication number: 20130293212
    Abstract: A modulator with balanced slope compensation including a control network, a slope compensation network, an offset network and an adjust network. The control network receives a feedback signal indicative of an output voltage and provides a loop control signal. The slope compensation network develops a slope compensation signal. The offset network determines a DC offset of the slope compensation signal. The adjust network combines the DC offset, the slope compensation signal and the loop control signal to provide a balanced slope compensated control signal. The DC offset may be determined as a peak of the slope compensation signal. The slope compensation signal may be developed based on the output voltage and a pulse control signal, in which the pulse control signal is developed using the balanced slope compensated control signal.
    Type: Application
    Filed: June 28, 2012
    Publication date: November 7, 2013
    Applicant: INTERSIL AMERICAS LLC
    Inventors: Rhys S.A. Philbrick, Steven P. Laur, M. Jason Houston
  • Patent number: 8487593
    Abstract: A controller for a switched mode power supply converting an input voltage to a regulated output voltage according to one embodiment includes a control network and a detection network. The control network develops a pulse width control signal for regulating a level of the output voltage. The detection network detects a phase lag of the output voltage and adjusts operation of the control network based on the phase lag. The phase lag may be determined from any parameter incorporating phase shift, such as the output voltage or the compensation voltage. Various alternative schemes are disclosed for adjusting the control loop, including, but not limited to, adding slope compensation, adjusting window resistance or window current, adding adjustment current to adjust ripple voltage, adjusting ripple transconductance, and adjusting ripple capacitance. Digital and analog compensation adjustment schemes are disclosed.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: July 16, 2013
    Assignee: Intersil Americas Inc.
    Inventors: Steven P. Laur, Rhys S. A. Philbrick
  • Publication number: 20130127557
    Abstract: A variable frequency modulator including a compensation network, first and second pulse control networks and a linearity controller. The compensation network is configured to provide a compensation signal indicative of an output load condition. The first pulse control network is configured to initiate pulses on a pulse control signal and to adjust operating frequency based on changes of the compensation signal. The second pulse control network is configured to terminate the pulses on the pulse control signal based on a predetermined timing parameter. The linearity controller is configured to adjust timing of terminating the pulses based on a predetermined steady state operating frequency and an actual operating frequency to maintain modulator gain at a constant level.
    Type: Application
    Filed: June 29, 2012
    Publication date: May 23, 2013
    Applicant: INTERSIL AMERICAS LLC
    Inventors: M. Jason Houston, Steven P. Laur, Rhys S.A. Philbrick
  • Patent number: 8405368
    Abstract: A phase current sharing network for a current mode multiphase switching regulator. The multiphase switching regulator includes switching networks for developing phase currents of switching phase networks controlled by pulse control signals for converting an input voltage to an output voltage. The regulator develops the pulse control signals based on current control values and at least one trigger value. The phase current sharing network includes conversion networks and a phase current combining network. Each conversion network provides a phase current value based on a corresponding phase current, such as by directly or indirectly measuring real current or by synthetically developing the phase current value. The phase current combining network develops an average phase current value based on the phase current values, and subtracts the average phase current value from each phase current value to provide the current control values used to control the switching networks.
    Type: Grant
    Filed: September 9, 2010
    Date of Patent: March 26, 2013
    Assignee: Intersil Americas Inc.
    Inventors: Steven P. Laur, Rhys S. A. Philbrick
  • Patent number: 8344717
    Abstract: A switching regulator and controller and an electronic device using same are disclosed in which the controller includes a sense circuit, an error amplifier circuit, a filter and reference circuit, and a comparator circuit. The switching regulator includes a pulse switch circuit coupled to an output inductor for developing an output voltage. The sense circuit provides a sense signal indicative of current through the output inductor. The error amplifier circuit develops an error signal indicative of error of the output voltage. The filter and reference circuit high pass filters the sense signal to provide a filtered sense signal and which balances the filtered sense signal and the error signal at a common DC level. The comparator circuit develops a pulse control signal using the error signal and the filtered sense signal, where the pulse control signal is for controlling switching of the pulse switch circuit.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: January 1, 2013
    Assignee: Intersil Americas Inc.
    Inventors: Rhys S. A. Philbrick, Matthew B. Harris, Steven P. Laur
  • Patent number: 8299764
    Abstract: A controller integrated circuit for a switched mode regulator which converts an input voltage to an output voltage. The controller includes a phase pin, a modulation circuit and a filter. The modulation circuit is configured to regulate the output voltage using the input voltage and output voltage level information. The filter has an input coupled to the phase pin and an output providing the output voltage level information which approximates the output voltage based on phase pin voltage. Various filters are contemplated, including passive and active low pass filters and the like. A regulator using such a controller is disclosed. A method of determining a voltage level of an output voltage includes receiving a phase voltage from a phase pin coupled to the phase node, and filtering the phase voltage to provide an output sense voltage having a voltage level approximating the voltage level of the output voltage.
    Type: Grant
    Filed: February 4, 2010
    Date of Patent: October 30, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Steven P. Laur, Rhys S. A. Philbrick
  • Publication number: 20120212204
    Abstract: A controller for a switch mode regulator with discontinuous conduction mode (DCM) correction which includes a correction network and a modulator. The correction network detects a low load condition indicative of regulation error during DCM and asserts an adjust value indicative thereof. The modulator receives the adjust value and adjusts operation accordingly to improve regulation during DCM. The correction network receives or determines a regulation metric, such as periods between successive pulses of a pulse control signal, or a current sense signal indicative of load current, and compares the regulation metric with one or more thresholds for determining the level of adjustment. Adjustment may be made using one or more methods, such as adjusting pulse on-time, adjusting pulse off-time, adjusting frequency of operation, etc.
    Type: Application
    Filed: May 2, 2011
    Publication date: August 23, 2012
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Rhys S.A. Philbrick, Steven P. Laur
  • Publication number: 20120126773
    Abstract: A switching regulator and controller and an electronic device using same are disclosed in which the controller includes a sense circuit, an error amplifier circuit, a filter and reference circuit, and a comparator circuit. The switching regulator includes a pulse switch circuit coupled to an output inductor for developing an output voltage. The sense circuit provides a sense signal indicative of current through the output inductor. The error amplifier circuit develops an error signal indicative of error of the output voltage. The filter and reference circuit high pass filters the sense signal to provide a filtered sense signal and which balances the filtered sense signal and the error signal at a common DC level. The comparator circuit develops a pulse control signal using the error signal and the filtered sense signal, where the pulse control signal is for controlling switching of the pulse switch circuit.
    Type: Application
    Filed: January 31, 2012
    Publication date: May 24, 2012
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Rhys S.A. Philbrick, Matthew B. Harris, Steven P. Laur
  • Patent number: 8154268
    Abstract: A controller for a switching regulator is disclosed including a sense circuit, an error amplifier circuit, a filter and reference circuit, and a comparator circuit. The switching regulator includes a pulse switch circuit coupled to an output inductor for developing an output voltage. The sense circuit provides a sense signal indicative of current through the output inductor. The error amplifier circuit develops an error signal indicative of error of the output voltage. The filter and reference circuit high pass filters the sense signal to provide a filtered sense signal, and references the filtered sense signal and the error signal to a common DC level. The comparator circuit develops a pulse control signal used to control switching of the pulse switch circuit based on comparing the error signal with the filtered sense signal.
    Type: Grant
    Filed: November 26, 2008
    Date of Patent: April 10, 2012
    Assignee: Intersil Americas Inc.
    Inventors: Rhys S. A. Philbrick, Matthew B. Harris, Steven P. Laur
  • Publication number: 20110260703
    Abstract: A controller for a switched mode power supply converting an input voltage to a regulated output voltage according to one embodiment includes a control network and a detection network. The control network develops a pulse width control signal for regulating a level of the output voltage. The detection network detects a phase lag of the output voltage and adjusts operation of the control network based on the phase lag. The phase lag may be determined from any parameter incorporating phase shift, such as the output voltage or the compensation voltage. Various alternative schemes are disclosed for adjusting the control loop, including, but not limited to, adding slope compensation, adjusting window resistance or window current, adding adjustment current to adjust ripple voltage, adjusting ripple transconductance, and adjusting ripple capacitance. Digital and analog compensation adjustment schemes are disclosed.
    Type: Application
    Filed: September 30, 2010
    Publication date: October 27, 2011
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Steven P. Laur, Rhys S.A. Philbrick
  • Publication number: 20110234193
    Abstract: A phase current sharing network for a current mode multiphase switching regulator. The multiphase switching regulator includes switching networks for developing phase currents of switching phase networks controlled by pulse control signals for converting an input voltage to an output voltage. The regulator develops the pulse control signals based on current control values and at least one trigger value. The phase current sharing network includes conversion networks and a phase current combining network. Each conversion network provides a phase current value based on a corresponding phase current, such as by directly or indirectly measuring real current or by synthetically developing the phase current value. The phase current combining network develops an average phase current value based on the phase current values, and subtracts the average phase current value from each phase current value to provide the current control values used to control the switching networks.
    Type: Application
    Filed: September 9, 2010
    Publication date: September 29, 2011
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Steven P. Laur, Rhys S.A. Philbrick
  • Publication number: 20100270995
    Abstract: A controller integrated circuit for a switched mode regulator which converts an input voltage to an output voltage. The controller includes a phase pin, a modulation circuit and a filter. The modulation circuit is configured to regulate the output voltage using the input voltage and output voltage level information. The filter has an input coupled to the phase pin and an output providing the output voltage level information which approximates the output voltage based on phase pin voltage. Various filters are contemplated, including passive and active low pass filters and the like. A regulator using such a controller is disclosed. A method of determining a voltage level of an output voltage includes receiving a phase voltage from a phase pin coupled to the phase node, and filtering the phase voltage to provide an output sense voltage having a voltage level approximating the voltage level of the output voltage.
    Type: Application
    Filed: February 4, 2010
    Publication date: October 28, 2010
    Applicant: INTERSIL AMERICAS INC.
    Inventors: Steven P. Laur, Rhys S.A. Philbrick