Abstract: A processor core is coupled to a memory hierarchy. The processor core is configured to execute vector floating-point instructions and micro-operations. A vector floating-point instruction is decoded. The decoding includes replacing the vector floating-point instruction with one or more vector floating-point micro-operations (VFPMs). A reorder buffer assigns a reorder buffer ID (ROBID) to each of the one or more VFPMs, in which the assigning includes a micro-sequencer ID (MSID). The processor core executes the one or more VFPMs. The executing includes requiring, by a first VFPM within the one or more VFPMs, a first update to an architectural floating-point flag. The architectural floating-point flag is set, based on the first update. The setting occurs after the one or more VFPMs have been committed by the processor core. A temporary floating-point flag is revised. The revising is based on the first update.

Abstract: A processor core is accessed. The processor core supports atomic memory operations. The atomic memory operations include multi-operand operations. A compare and swap (CAS) instruction is issued in the processor core. The CAS instruction necessitates three source operands. One of the source operands comprises a destination register. The CAS instruction is split into a plurality of micro-operations. A first value is written from a memory location indicated by a first source operand into a temporary register. A memory word location addressed by a second source operand is accessed using a second micro-operation. The first micro-operation and the second micro-operation are interlocked. Contents of the memory word location are compared. A third source operand is stored to the memory word location addressed by the second source operand. The storing is based on a match of the comparing.

Abstract: A processor core is accessed. The processor core supports virtual memory addressing. The processor core includes a memory management unit (MMU) and a load store unit (LSU). A page table walk is performed by the MMU. The page table walk is responsive to a memory operation. The page table walk identifies a page table entry (PTE) for a virtual to physical address translation. The PTE is read. The reading obtains a first value from the PTE and includes determining, by the MMU, to update one or more status bits within the PTE. The PTE is re-read. The re-reading obtains a second value from the PTE. The PTE is updated to include the one or more status bits, based on a match between the first and second value. The updated PTE is stored in a page table. The re-reading, the updating, and the storing are performed atomically.

Abstract: Disclosed embodiments provide techniques for instruction execution with a processor pipeline for data transfer operations. A processor core is accessed. The processor core executes one or more instructions out of order. The processor core supports integer operations and floating-point operations. An instruction in the processor core is decoded. The instruction is a data transfer operation. The data transfer operation necessitates a floating-point operation and an integer operation. The floating-point operation and the integer operation are dispatched to one or more issue queues. The floating-point operation and the integer operation are interlocked. The interlocking is accomplished using at least one entry in the one or more issue queues. A first operation of the floating-point operation and the integer operation is executed. A second operation of the floating-point operation and the integer operation is executed. The execution of the second operation is based on the interlocking.

Abstract: Disclosed techniques enable processors that are capable of performing a wide range of vector operations. A processor can support multiple types of instructions. The instructions can include one or more operands, and the one or more operands can include different data types. An A-type instruction can have dependencies on a B-type instruction. An A-type instruction includes a vector instruction. A B-type instruction includes an integer instruction or a floating-point instruction. A datapath is provided to enable intermediate results from a B-type instruction to be supplied to the A-type instruction on which it depends, without utilizing register file resources, such as general-purpose register (GPR) register resources. Vector instruction performance is thereby enabled without the additional resources used with GPR register access.

Abstract: A method of producing human astrocytes from neural stem cells (NSCs) involves providing induced progenitor cells (iPSCs), differentiating iPSCs to neural stem cells (NSCs), and differentiating NSCs to astrocytes.

Abstract: Techniques for instruction execution, in a processor supporting vector operations, are disclosed. A processor core is accessed. The processor core supports vector operations and is configured to execute micro-operations. A vector load operation is issued. It includes a first number of vector elements, which is determined by a vector length control (VL) register. The vector load operation is split into a series of micro-operations, in which each micro-operation corresponds to a unique vector element and is assigned an element order value. The micro-operations are executed out of order. At least one fault is detected. An earliest faulting micro-operation is determined, based on the element order value of each of the micro-operations. The VL register is updated, based on the earliest faulting micro-operation. All micro-operations that were assigned an element order value higher than an element order value that was assigned to the earliest faulting micro-operation are cancelled.

Abstract: Techniques for vector instruction operation are disclosed. A processor core is accessed. The processor core supports vector operations, the processor core includes an execution pipeline, and the execution pipeline is configured to execute micro-operations. A vector operation is issued, in the processor core. The vector operation necessitates a plurality of execution cycles. The vector operation is split into a series of micro-operations. Execution of the series of micro-operations is initiated. An operation exception is received by the processor core. The operation exception is processed. Execution of the series of micro-operations is completed, based on the timing of the operation exception. The splitting, the initiating, and the completing are performed by a micro-operation sequencer within a decode unit of the processor core. The micro-operation sequencer assigns the series of micro-operations, based on a type of the vector operation.

Abstract: Techniques for processor management are disclosed. One or more processors are accessed. The one or more processors include one or more logical partitions. A processor from the one or more processors executes one or more instructions out of order. The processor detects a deadlock condition. The deadlock condition prevents the one or more instructions from completing. The deadlock condition occurs in a logical partition within the one or more logical partitions. A parallelism of execution in the logical partition is reduced. The reducing allows the one or more instructions to complete. The reducing is based on one or more control bits. Cessation of the deadlock condition is recognized. The parallelism of execution in the logical partition is restored. The restoring is based on the one or more control bits. The one or more instructions execute on one or more threads running on the processor.

Abstract: A wheel cover for a wheel of a vehicle may include a cover portion removably operably coupleable to the wheel via a first set of retention tabs, the cover portion may be centered at an axis of rotation of the wheel and may cover spokes of the wheel, and a button cap removably operably coupleable to the wheel cover via a second set of retention tabs, the button cap may be centered at the axis of rotation of the wheel. The first set of retention tabs may be urged by a wire ring into engagement with a lip of the wheel, the lip may extend around the axis of rotation at a center bore of the wheel. The second set of retention tabs may insert into corresponding ones of a set of retention slots disposed in the cover portion.

Abstract: Techniques for debugging errors in a processor are disclosed. One or more processors are accessed. Each processor within the one or more processors includes a set of assertion registers. A processor within the one or more processors executes one or more instructions. An assertion logic detects an error condition in the processor. The detecting occurs during the executing. The error condition is recorded. The recording is based on one or more bits in the set of assertion registers. A hardware interface reads the one or more bits in the set of assertion registers. The one or more bits indicate the error condition to the hardware interface. The executing includes a communication protocol between the processor and a slave device. The error condition comprises an incorrect value in a credit buffer. The credit buffer controls a number of transactions allowed between the processor and the slave device.

Abstract: Disclosed embodiments provide techniques for instruction execution with a processor pipeline for data transfer operations. A processor core is accessed. The processor core executes one or more instructions out of order. The processor core supports integer operations and floating-point operations. An instruction in the processor core is decoded. The instruction is a data transfer operation. The data transfer operation necessitates a floating-point operation and an integer operation. The floating-point operation and the integer operation are dispatched to one or more issue queues. The floating-point operation and the integer operation are interlocked. The interlocking is accomplished using at least one entry in the one or more issue queues. A first operation of the floating-point operation and the integer operation is executed. A second operation of the floating-point operation and the integer operation is executed. The execution of the second operation is based on the interlocking.

Abstract: Disclosed embodiments provide techniques for instruction execution in computer processors. A dispatch unit dispatches instructions to one or more issue queues. Instructions from the issue queues feed into execution pipelines. Each execution pipeline includes instruction queue control logic, and two execution engines. A first execution engine is assigned to variable latency instructions while a second execution engine is assigned to fixed latency instructions. While a variable latency instruction executes, fixed latency instructions can be issued, executed, and completed. When the variable latency instruction finishes execution, a request is issued by the first execution engine to the instruction queue control logic. In response, the instruction queue control logic introduces a stall in a common write-back pipeline, allowing the variable latency instruction to complete. The result of the variable latency instruction is provided to a depending fixed latency instruction via a bypass path.

Abstract: Disclosed techniques enable processors that are capable of performing a wide range of vector operations. A processor can support multiple types of instructions. The instructions can include one or more operands, and the one or more operands can include different data types. An A-type instruction can have dependencies on a B-type instruction. An A-type instruction includes a vector instruction. A B-type instruction includes an integer instruction or a floating-point instruction. A datapath is provided to enable intermediate results from a B-type instruction to be supplied to the A-type instruction on which it depends, without utilizing register file resources, such as general-purpose register (GPR) register resources. Vector instruction performance is thereby enabled without the additional resources used with GPR register access.

Abstract: A surgical drainage system is disclosed that includes an assay device operatively coupled to a surgical drainage tube. The drainage tube is configured for implantation within a surgical bed of a subject to drain surgical drain fluid out of the surgical bed. The assay device is configured to detect at least one analyte within the drainage fluid. The at least one analyte is indicative of a surgical bed condition.

Abstract: Techniques for instruction execution based on processor instruction exception handling are disclosed. A processor core is accessed. The processor core executes at least one instruction thread. The processor core executes one or more instructions out of order. An ordered list of instructions is maintained. The ordered list is based on instructions that are presented to the processor core for execution. The ordered list is organized using one or more pointers. An execution exception is detected in the processor core. The execution exception corresponds to one of the instructions in the ordered list. The execution exception requires initiating an exception handling routine. An effective age of an instruction in the ordered list is determined. The effective age corresponds to the execution exception. The exception handling routine is initiated, based on matching the effective age of an instruction in the ordered list with one of the one or more pointers.

Abstract: A method for detecting minimal residual disease in a subject following a cancer surgery is disclosed. The method includes obtaining a sample from the subject. The sample includes a surgical drainage. The method also includes isolating an amount of tumor-associated genetic material from the sample, sequencing the amount of tumor-associated genetic material to detect and quantify at least one tumor-associated mutation or variant in the amount of tumor-associated genetic material, and providing the at least one quantity of the at least one tumor-associated mutation or variant to a practitioner.

Abstract: Various embodiments include apparatus, systems, and methods relating to protective packaging for shipping items. In some embodiments, a protective packaging system may include a shipping container and a foam insert assembly. The shipping container may encase an interior portion. The foam insert assembly may be configured to conformally encapsulate one or more shipping items within the interior portion of the shipping container, e.g., so as to protect the one or more shipping items from mechanical impact damage (e.g., bending) and/or environmental damage (e.g., exposure to moisture) during shipping.

Abstract: Techniques related to improving performance of an automated control system for drilling with a drilling system, comprising directing drilling tools on a drilling rig to drill, a borehole using the automated control system, obtaining, from one or more surface sensors disposed at a surface of the drilling site, surface sensor data relating to surface drilling activity of the drilling system, determining, based on a comparison between the surface sensor data and a set of historical data, a set of drilling parameters associated with a drilling state, applying the set of drilling parameters to a physics model of the drilling site to determine a set of downhole parameters for the drilling site, wherein the physics model comprises a simulation of current conditions of the borehole and a drill string of the drilling rig, and adjusting operation of at least one of the drilling tools based on the set of downhole parameters.

Abstract: A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.