Abstract: A finishing device which is configured to receive sheets of imaging media, forming a sheet stack, from an imaging apparatus includes a sheet stack tray to support the sheet stack. The finishing device also includes a sheet stack hold-down device which is operable from a first position to a variable second position. When the hold-down device is in the second position it presses the sheet stack against the sheet stack tray. The finishing device further includes a sensor which can detect the position of the sheet stack hold-down device when it is in the second position, to thereby provide an approximation of the thickness of the sheet stack, based on the then-current second position of the hold-down device.

Abstract: The present invention is a method and apparatus for processing full exceptions in a partial parallel processor operating on parallel operands which form into N groups. The method comprising: (a) generating P partial exception states for P partial exceptions from the partial parallel processor operating on the N groups of the parallel operands; the P partial exceptions correspond to the full exceptions; and (b) handling the P partial exceptions based on the P partial exception states.

Abstract: A network content service apparatus includes a set of compute elements adapted to perform a set of network services; and a switching fabric coupling compute elements in said set of compute elements. The set of network services includes firewall protection, Network Address Translation, Internet Protocol forwarding, bandwidth management, Secure Sockets Layer operations, Web caching, Web switching, and virtual private networking. Code operable on the compute elements enables the network services, and the compute elements are provided on blades which further include at least one input/output port.

Abstract: A multi-processor includes multiple processing clusters for performing assigned applications. Each cluster includes a set of compute engines, with each compute engine coupled to a set of cache memory. A compute engine includes a central processing unit and a coprocessor with a set of application engines. The central processing unit and coprocessor are coupled to the compute engine's associated cache memory. The sets of cache memory within a cluster are also coupled to one another.

Abstract: A multi-processor includes multiple processing clusters for performing assigned applications. Each cluster includes a set of compute engines, with each compute engine coupled to a set of cache memory. A compute engine includes a central processing unit and a coprocessor with a set of application engines. The central processing unit and coprocessor are coupled to the compute engine's associated cache memory. The sets of cache memory within a cluster are also coupled to one another.

Abstract: A multi-processor includes multiple processing clusters for performing assigned applications. Each cluster includes a set of compute engines, with each compute engine coupled to a set of cache memory. A compute engine includes a central processing unit and a coprocessor with a set of application engines. The central processing unit and coprocessor are coupled to the compute engine's associated cache memory. The sets of cache memory within a cluster are also coupled to one another.

Abstract: A multi-processor includes multiple processing clusters for performing assigned applications. Each cluster includes a set of compute engines, with each compute engine coupled to a set of cache memory. A compute engine includes a central processing unit and a coprocessor with a set of application engines. The central processing unit and coprocessor are coupled to the compute engine's associated cache memory. The sets of cache memory within a cluster are also coupled to one another.

Abstract: A multi-processor includes multiple processing clusters for performing assigned applications. Each cluster includes a set of compute engines, with each compute engine coupled to a set of cache memory. A compute engine includes a central processing unit and a coprocessor with a set of application engines. The central processing unit and coprocessor are coupled to the compute engine's associated cache memory. The sets of cache memory within a cluster are also coupled to one another.

Abstract: A sheet separating device having a mechanism for buckling or humping a top sheet of a stack and thereby separating the top sheet from an underlying sheet that may be adhering to the underside of said top sheet.

Abstract: A sheet separating device having a mechanism for buckling or humping a top sheet of a stack and thereby separating the top sheet from an underlying sheet that may be adhering to the underside of said top sheet.

Abstract: An executed first instruction having a first logical operand as a destination is retired. A register assigned to the first logical operand is identified to back out of an architectural state. The identifying may be performed when an executed second instruction having a second logical operand as a destination is ready to retire or is retired. The register may be assigned to a third logical operand for an instruction to be executed.

Abstract: A processor having a plurality of registers is provided. The processor is capable of re-executing at least one selected instruction by backing out of an architectural register state. A method is provided for backing a processor out of an architectural state. The method comprises reassigning a register to a logical operand of an instruction, the register having been assigned to the logical operand in a previous architectural state; and re-executing the instruction.

Abstract: A microprocessor capable of delaying the deallocation of an arithmetic flags register is described. A system processes instructions of a first instruction set architecture which has an arithmetic flags register. The system also processes instructions of a second instruction set architecture which is not compatible with the first instruction set architecture. In order to process a first instruction of the first instruction set architecture that implicitly updates the arithmetic flags register, the arithmetic flags register shares a physical destination register with a general register containing a result for the first instruction. An instruction that does not update the arithmetic flags but would deallocate the register containing the arithmetic flags triggers the delayed deallocation mechanism of the present invention.

Abstract: A fabric for use in an architectural covering device includes a plurality of elongated vanes preferably of tubular configuration having a pair of flaps extending longitudinally along the entire length of the vane. A continuous face sheet material has elongated folds at spaced intervals that are secured along the flaps of the vanes so as to pivotally connect the vanes to the face sheet material at predetermined spaced intervals. The fabric is adapted to be supported with an operational system in an architectural opening so that if the vanes are suspended vertically they are slidably movable laterally of the window opening and pivotally movable about vertical longitudinal axes to extend and retract as well as open and close the covering. An apparatus and method for forming the fabric is also disclosed as well as systems for finishing the endmost vanes in the fabric.