Patents by Inventor Rich Fogal

Rich Fogal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11398465
    Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.
    Type: Grant
    Filed: June 13, 2019
    Date of Patent: July 26, 2022
    Assignee: Micron Technology, Inc.
    Inventors: Rich Fogal, Owen R. Fay
  • Publication number: 20190296003
    Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.
    Type: Application
    Filed: June 13, 2019
    Publication date: September 26, 2019
    Inventors: Rich Fogal, Owen R. Fay
  • Patent number: 10381336
    Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.
    Type: Grant
    Filed: July 26, 2018
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Rich Fogal, Owen R. Fay
  • Publication number: 20180331089
    Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.
    Type: Application
    Filed: July 26, 2018
    Publication date: November 15, 2018
    Inventors: Rich Fogal, Owen R. Fay
  • Patent number: 10062678
    Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.
    Type: Grant
    Filed: February 1, 2017
    Date of Patent: August 28, 2018
    Assignee: Micron Technologies, Inc.
    Inventors: Rich Fogal, Owen R. Fay
  • Publication number: 20170141096
    Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.
    Type: Application
    Filed: February 1, 2017
    Publication date: May 18, 2017
    Inventors: Rich Fogal, Owen R. Fay
  • Patent number: 9595513
    Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: March 14, 2017
    Assignee: Micron Technology, Inc.
    Inventors: Rich Fogal, Owen R. Fay
  • Publication number: 20160155729
    Abstract: Proximity coupling interconnect packaging systems and methods. A semiconductor package assembly comprises a substrate, a first semiconductor die disposed adjacent the substrate, and a second semiconductor die stacked over the first semiconductor die. There is at least one proximity coupling interconnect between the first semiconductor die and the second semiconductor die, the proximity coupling interconnect comprising a first conductive pad on the first coupling face on the first semiconductor die and a second conductive pad on a second coupling face of the second semiconductor die, the second conductive pad spaced apart from the first conductive pad by a gap distance and aligned with the first conductive pad. An electrical connector is positioned laterally apart from the proximity coupling interconnect and extends between the second semiconductor die and the substrate, the position of the electrical connector defining the alignment of the first conductive pad and the second conductive pad.
    Type: Application
    Filed: December 1, 2014
    Publication date: June 2, 2016
    Inventors: Rich Fogal, Owen R. Fay
  • Patent number: 8987885
    Abstract: Microdevices and methods for packaging microdevices. One embodiment of a packaged microdevice includes a substrate having a mounting area, contacts in the mounting area, and external connectors electrically coupled to corresponding contacts. The microdevice also includes a die located across from the mounting area and spaced apart from the substrate by a gap. The die has an integrated circuit and pads electrically coupled to the integrated circuit. The microdevice further includes first and second conductive elements in the gap that form interconnects between the contacts of the substrate and corresponding pads of the die. The first conductive elements are electrically connected to contacts on the substrate, and the second conductive elements are electrically coupled to corresponding pads of the die.
    Type: Grant
    Filed: January 15, 2013
    Date of Patent: March 24, 2015
    Assignee: Micron Technology, Inc.
    Inventors: Stuart L. Roberts, Tracy V. Reynolds, Rich Fogal, Matt E. Schwab
  • Patent number: 8354301
    Abstract: Microdevices and methods for packaging microdevices. One embodiment of a packaged microdevice includes a substrate having a mounting area, contacts in the mounting area, and external connectors electrically coupled to corresponding contacts. The microdevice also includes a die located across from the mounting area and spaced apart from the substrate by a gap. The die has an integrated circuit and pads electrically coupled to the integrated circuit. The microdevice further includes first and second conductive elements in the gap that form interconnects between the contacts of the substrate and corresponding pads of the die. The first conductive elements are electrically connected to contacts on the substrate, and the second conductive elements are electrically coupled to corresponding pads of the die.
    Type: Grant
    Filed: January 10, 2011
    Date of Patent: January 15, 2013
    Assignee: Micron Technology, Inc.
    Inventors: Stuart L. Roberts, Tracy V. Reynolds, Rich Fogal, Matt E. Schwab
  • Patent number: 7977597
    Abstract: Wire bonders and methods of wire-bonding are disclosed herein. In one embodiment, a method includes attaching a wire to a terminal of a microelectronic component and generating an arc between a first electrode and a second electrode to sever the wire at a point at least proximate to the first and second electrodes. In another embodiment, a wire bonder includes a bond head having a capillary, a first electrode and a second electrode each disposed relative to the bond head, and a controller operably coupled to the first and second electrodes. The controller has a computer-readable medium containing instructions to perform the above-mentioned method.
    Type: Grant
    Filed: June 5, 2007
    Date of Patent: July 12, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Stuart L. Roberts, Rich Fogal
  • Publication number: 20110104857
    Abstract: Microdevices and methods for packaging microdevices. One embodiment of a packaged microdevice includes a substrate having a mounting area, contacts in the mounting area, and external connectors electrically coupled to corresponding contacts. The microdevice also includes a die located across from the mounting area and spaced apart from the substrate by a gap. The die has an integrated circuit and pads electrically coupled to the integrated circuit. The microdevice further includes first and second conductive elements in the gap that form interconnects between the contacts of the substrate and corresponding pads of the die. The first conductive elements are electrically connected to contacts on the substrate, and the second conductive elements are electrically coupled to corresponding pads of the die.
    Type: Application
    Filed: January 10, 2011
    Publication date: May 5, 2011
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: Stuart L. Roberts, Tracy V. Reynolds, Rich Fogal, Matt E. Schwab
  • Patent number: 7868440
    Abstract: Microdevices and methods for packaging microdevices. One embodiment of a packaged microdevice includes a substrate having a mounting area, contacts in the mounting area, and external connectors electrically coupled to corresponding contacts. The microdevice also includes a die located across from the mounting area and spaced apart from the substrate by a gap. The die has an integrated circuit and pads electrically coupled to the integrated circuit. The microdevice further includes first and second conductive elements in the gap that form interconnects between the contacts of the substrate and corresponding pads of the die. The first conductive elements are electrically connected to contacts on the substrate, and the second conductive elements are electrically coupled to corresponding pads of the die.
    Type: Grant
    Filed: August 25, 2006
    Date of Patent: January 11, 2011
    Assignee: Micron Technology, Inc.
    Inventors: Stuart L. Roberts, Tracy V. Reynolds, Rich Fogal, Matt E. Schwab
  • Publication number: 20080053964
    Abstract: Wire bonders and methods of wire-bonding are disclosed herein. In one embodiment, a method includes attaching a wire to a terminal of a microelectronic component and generating an arc between a first electrode and a second electrode to sever the wire at a point at least proximate to the first and second electrodes. In another embodiment, a wire bonder includes a bond head having a capillary, a first electrode and a second electrode each disposed relative to the bond head, and a controller operably coupled to the first and second electrodes. The controller has a computer-readable medium containing instructions to perform the above-mentioned method. It is emphasized that this Abstract is provided to comply with the rules requiring an abstract. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
    Type: Application
    Filed: June 5, 2007
    Publication date: March 6, 2008
    Applicant: Micron Technology, Inc.
    Inventors: Stuart Roberts, Rich Fogal
  • Publication number: 20080048316
    Abstract: Microdevices and methods for packaging microdevices. One embodiment of a packaged microdevice includes a substrate having a mounting area, contacts in the mounting area, and external connectors electrically coupled to corresponding contacts. The microdevice also includes a die located across from the mounting area and spaced apart from the substrate by a gap. The die has an integrated circuit and pads electrically coupled to the integrated circuit. The microdevice further includes first and second conductive elements in the gap that form interconnects between the contacts of the substrate and corresponding pads of the die. The first conductive elements are electrically connected to contacts on the substrate, and the second conductive elements are electrically coupled to corresponding pads of the die.
    Type: Application
    Filed: August 25, 2006
    Publication date: February 28, 2008
    Applicant: Micron Technology, Inc.
    Inventors: Stuart L. Roberts, Tracy V. Reynolds, Rich Fogal, Matt E. Schwab
  • Patent number: 7227095
    Abstract: Wire bonders and methods of wire-bonding are disclosed herein. In one embodiment, a method includes attaching a wire to a terminal of a microelectronic component and generating an arc between a first electrode and a second electrode to sever the wire at a point at least proximate to the first and second electrodes. In another embodiment, a wire bonder includes a bond head having a capillary, a first electrode and a second electrode each disposed relative to the bond head, and a controller operably coupled to the first and second electrodes. The controller has a computer-readable medium containing instructions to perform the above-mentioned method.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: June 5, 2007
    Assignee: Micron Technology, Inc.
    Inventors: Stuart L. Roberts, Rich Fogal
  • Publication number: 20060121650
    Abstract: A method used to form a semiconductor device comprises providing first and second circuit portions having first and second pad portions respectively. The second circuit portion is electrically isolated from the first circuit portion. The first and second pad portions are then electrically connected, for example with a ball bond or a wire bond, to electrically couple the first and second circuit portions. In various embodiments the semiconductor device will not function until the pad portions are electrically coupled, and in other embodiments the functionality of the device may be selectively controlled by connecting selected pad portions from a plurality of pad portions. Isolating the first and second circuit portions allows electrical operations such as antifuse programming to be carried out without adversely affecting related circuits. Once electrical operations are completed, the isolated circuit portions are electrically coupled to provide a complete circuit.
    Type: Application
    Filed: January 31, 2006
    Publication date: June 8, 2006
    Inventors: Rich Fogal, Tracy Reynolds, Timothy Cowles
  • Patent number: 6991970
    Abstract: A method used to form a semiconductor device comprises providing first and second circuit portions having first and second pad portions respectively. The second circuit portion is electrically isolated from the first circuit portion. The first and second pad portions are then electrically connected, for example with a ball bond or a wire bond, to electrically couple the first and second circuit portions. In various embodiments the semiconductor device will not function until the pad portions are electrically coupled, and in other embodiments the functionality of the device may be selectively controlled by connecting selected pad portions from a plurality of pad portions. Isolating the first and second circuit portions allows electrical operations such as antifuse programming to be carried out without adversely affecting related circuits. Once electrical operations are completed, the isolated circuit portions are electrically coupled to provide a complete circuit.
    Type: Grant
    Filed: August 30, 2001
    Date of Patent: January 31, 2006
    Assignee: Micron Technology, Inc.
    Inventors: Rich Fogal, Tracy Reynolds, Timothy Cowles
  • Patent number: 6886734
    Abstract: A wire-bonding machine includes a heat block for supporting a lead frame during wire-bonding. A clamp mechanism in the machine clamps leads of the lead frame during wire-bonding by fixedly holding sets of the leads against the heat block one set at a time. A wire-bonding tool wire-bonds leads clamped by the clamp mechanism to bond pads on an integrated circuit die. By clamping leads of the lead frame in separate sets, the machine provides improved clamping for lead frames with leads requiring clamping in different planes.
    Type: Grant
    Filed: July 22, 2002
    Date of Patent: May 3, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Michael B. Ball, Rich Fogal
  • Patent number: 6884657
    Abstract: An offset die stacking arrangement is disclosed having at least one upper level die having a width which is less than the distance separating the opposing bonding sites of the underlying die. The upper die is fixed above the lower die and rotated within a plane parallel to the lower die through an angle which insures that none of the bonding sites of the lower die are obstructed by the upper die. Once the dice are fixed in this manner, the entire assembly is subjected to the wire bonding process with all of the bonds being made in the same step.
    Type: Grant
    Filed: October 21, 1999
    Date of Patent: April 26, 2005
    Assignee: Micron Technology, Inc.
    Inventors: Rich Fogal, Michael B. Ball