Patents by Inventor Richard A. Blanchard

Richard A. Blanchard has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10777670
    Abstract: An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n-epi layer, a p-well, vertical insulated gate regions formed in the p-well, and an n? layer over the p-well and between the gate regions, so that vertical npn and pnp transistors are formed. After forming the p-well, boron ions are implanted into the exposed surface of the p-well to form a p+ region. The n-epi layer is then grown over the p-well and the p+ region, and the boron in the p+ region is diffused upward into the n-epi layer and downward to form an intermediate p+ region. The p-well's highly doped intermediate region enables improvement in the npn transistor efficiency as well as enabling more independent control over the characteristics of the n-type layer (emitter) and the overall dopant concentration and thickness of the p-type base to optimize the thyristor's performance.
    Type: Grant
    Filed: May 29, 2019
    Date of Patent: September 15, 2020
    Assignee: Pakal Technologies, Inc.
    Inventors: Hidenori Akiyama, Richard A. Blanchard
  • Publication number: 20200279926
    Abstract: Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.
    Type: Application
    Filed: December 5, 2019
    Publication date: September 3, 2020
    Applicant: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Hamza Yilmaz, Richard A. Blanchard
  • Patent number: 10755060
    Abstract: In one embodiment, a printed security mark comprises a random arrangement of printed LEDs and a wavelength conversion layer. During fabrication of the mark, the LEDs are energized, and the resulting dot pattern is converted into a unique digital first code and stored in a database. The emitted spectrum vs. intensity and persistence of the wavelength conversion layer is also encoded in the first code. The mark may be on a credit card, casino chip, banknote, passport, etc. to be authenticated. For authenticating the mark, the LEDs are energized and the dot pattern, spectrum vs. intensity, and persistence are converted into a code and compared to the first code stored in the database. If there is a match, the mark is authenticated.
    Type: Grant
    Filed: June 13, 2018
    Date of Patent: August 25, 2020
    Assignee: NTHDEGREE TECHNOLOGIES WORLDWIDE INC.
    Inventors: Steven B. Roach, Richard A. Blanchard, Eric Kahrs, Larry Todd Biggs, Chye Kiat Ang, Mark D. Lowenthal, William J. Ray
  • Publication number: 20200243674
    Abstract: Dual-base two-sided bipolar power transistors which use an insulated field plate to separate the emitter/collector diffusions from the nearest base contact diffusion. This provides a surprising improvement in turn-off performance, and in breakdown voltage.
    Type: Application
    Filed: January 27, 2020
    Publication date: July 30, 2020
    Applicant: Ideal Power, Inc.
    Inventors: William C. Alexander, Richard A. Blanchard
  • Patent number: 10720511
    Abstract: Methods and systems for power semiconductor devices integrating multiple trench transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.
    Type: Grant
    Filed: October 1, 2018
    Date of Patent: July 21, 2020
    Assignee: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
  • Patent number: 10720510
    Abstract: Methods and systems for power semiconductor devices integrating multiple quasi-vertical transistors on a single chip. Multiple power transistors (or active regions) are paralleled, but one transistor has a lower threshold voltage. This reduces the voltage drop when the transistor is forward-biased. In an alternative embodiment, the power device with lower threshold voltage is simply connected as a depletion diode, to thereby shunt the body diodes of the active transistors, without affecting turn-on and ON-state behavior.
    Type: Grant
    Filed: May 9, 2018
    Date of Patent: July 21, 2020
    Assignee: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
  • Patent number: 10636772
    Abstract: Over a flexible substrate are deposited stacked pixel layers including a bottom layer of LEDs forming blue pixels, a middle layer of LEDs forming green pixels, and a top layer of LEDs forming red pixels. The pixels are substantially transparent, due to the LEDs being microscopic and the pixel areas being much larger, to allow light from the underlying layers to pass through. The three layers of pixels are aligned so that a combination of a single top red pixel, a single underlying green pixel, and a single underlying blue pixel form a single multi-color pixel. The different layers have transparent column and row lines.
    Type: Grant
    Filed: August 20, 2019
    Date of Patent: April 28, 2020
    Assignee: NTHDEGREE TECHNOLOGIES WORLDWIDE INC.
    Inventors: William Johnstone Ray, Michael LeFebvre, Darin Wagner, Richard A. Blanchard
  • Publication number: 20200111672
    Abstract: Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.
    Type: Application
    Filed: October 3, 2018
    Publication date: April 9, 2020
    Applicant: Ideal Power Inc.
    Inventors: Richard A. Blanchard, William C. Alexander
  • Publication number: 20200105873
    Abstract: A high power vertical insulated-gate switch is described that includes a parallel cell array having inner cells and an edge cell. The cells have a vertical npnp structure with a trenched field effect device that turns the device on and off. The edge cell is prone to breaking down at high currents. Techniques used to cause the current in the edge cell to be lower than the current in the inner cells, to improve robustness, include: forming a top n-type source region to not extend completely across opposing trenches in areas of the edge cell; forming the edge cell to have a threshold voltage of its field effect device that is greater than the threshold voltage of the field effect devices in the inner cells; and providing a resistive layer between the edge cell and a top cathode electrode electrically contacting the inner cells and the edge cell.
    Type: Application
    Filed: September 30, 2019
    Publication date: April 2, 2020
    Inventors: Richard A. Blanchard, Vladimir Rodov, Woytek Tworzydlo, Hidenori Akiyama
  • Publication number: 20200098856
    Abstract: Power devices using refilled trenches with permanent charge at or near their sidewalls. These trenches extend vertically into a drift region.
    Type: Application
    Filed: June 12, 2019
    Publication date: March 26, 2020
    Applicant: MaxPower Semiconductor Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Richard A. Blanchard
  • Patent number: 10600898
    Abstract: A vertical bidirectional insulated gate turn-off (IGTO) device includes a top half formed over a top surface of a substrate and a bottom half formed over the bottom surface of the substrate. A top electrode is formed over the top half, and a bottom electrode is formed over the bottom half. The layered structure forms vertical NPN and PNP transistors. Each half includes trenched gates. When a first polarity voltage is applied across the electrodes, one of the halves may be turned on by biasing its gates to conduct current between the top and bottom electrodes. When a voltage of an opposite polarity is applied across the electrodes, the other one of the halves may be turned on by biasing its gates to conduct current between the two electrodes. In one embodiment, biasing the gates increases the beta of the NPN transistor to turn on the device.
    Type: Grant
    Filed: February 18, 2019
    Date of Patent: March 24, 2020
    Assignee: Pakal Technologies, Inc.
    Inventors: Richard A. Blanchard, Vladimir Rodov
  • Patent number: 10593813
    Abstract: A new semiconductor rectifier structure. In general, a MOS-transistor-like structure is located above a JFET-like deeper structure. The present application teaches ways to combine and optimize these two structures in a merged device so that the resulting combined structure achieves both a low forward voltage and a high reverse breakdown voltage in a relatively small area. In one class of innovative implementations, an insulated (or partially insulated) trench is used to define a vertical channel in a body region along the sidewall of a trench, so that majority carriers from a “source” region (typically n+) can flow through the channel. An added “pocket” diffusion, of the same conductivity type as the body region (p-type in this example), provides an intermediate region around the bottom of the trench. This intermediate diffusion, and an additional deep region of the same conductivity type, define a deep JFET-like device which is in series with the MOS channel portion of the diode.
    Type: Grant
    Filed: June 22, 2018
    Date of Patent: March 17, 2020
    Assignee: MaxPower Semiconductor Inc.
    Inventors: Richard A. Blanchard, Mohamed N. Darwish, Jun Zeng
  • Patent number: 10580885
    Abstract: Dual-base two-sided bipolar power transistors which use an insulated field plate to separate the emitter/collector diffusions from the nearest base contact diffusion. This provides a surprising improvement in turn-off performance, and in breakdown voltage.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: March 3, 2020
    Assignee: Ideal Power, Inc.
    Inventors: William C. Alexander, Richard A. Blanchard
  • Publication number: 20200058780
    Abstract: Dual-base two-sided bipolar power transistors which use an insulated field plate to separate the emitter/collector diffusions from the nearest base contact diffusion. This provides a surprising improvement in turn-off performance, and in breakdown voltage.
    Type: Application
    Filed: August 30, 2019
    Publication date: February 20, 2020
    Applicant: Ideal Power, Inc.
    Inventors: William C. Alexander, Richard A. Blanchard
  • Patent number: 10529810
    Abstract: Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: January 7, 2020
    Assignee: MaxPower Semiconductor, Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Hamza Yilmaz, Richard A. Blanchard
  • Publication number: 20200006499
    Abstract: Methods and systems for lateral power devices, and methods for operating them, in which charge balancing is implemented in a new way. In a first inventive teaching, the lateral conduction path is laterally flanked by regions of opposite conductivity type which are self-aligned to isolation trenches which define the surface geometry of the channel. In a second inventive teaching, which can be used separately or in synergistic combination with the first teaching, the drain regions are self-isolated. In a third inventive teaching, which can be used in synergistic combination with the first and/or second teachings, the source regions are also isolated from each other. In a fourth inventive teaching, the lateral conduction path is also overlain by an additional region of opposite conductivity type.
    Type: Application
    Filed: December 9, 2016
    Publication date: January 2, 2020
    Applicant: MaxPower Semiconductor, Inc.
    Inventors: Mohamed N. Darwish, Jun Zeng, Hamza Yilmaz, Richard A. Blanchard
  • Publication number: 20190393331
    Abstract: An insulated gate turn-off thyristor has a layered structure including a p+ layer (e.g., a substrate), an n-epi layer, a p-well, vertical insulated gate regions formed in the p-well, and an n? layer over the p-well and between the gate regions, so that vertical npn and pnp transistors are formed. After forming the p-well, boron ions are implanted into the exposed surface of the p-well to form a p+ region. The n-epi layer is then grown over the p-well and the p+ region, and the boron in the p+ region is diffused upward into the n-epi layer and downward to form an intermediate p+ region. The p-well's highly doped intermediate region enables improvement in the npn transistor efficiency as well as enabling more independent control over the characteristics of the n-type layer (emitter) and the overall dopant concentration and thickness of the p-type base to optimize the thyristor's performance.
    Type: Application
    Filed: May 29, 2019
    Publication date: December 26, 2019
    Inventors: Hidenori Akiyama, Richard A. Blanchard
  • Patent number: 10516073
    Abstract: The present invention provides an electronic apparatus, such as a lighting device comprised of light emitting diodes (LEDs) or a power generating apparatus comprising photovoltaic diodes, which may be created through a printing process, using a semiconductor or other substrate particle ink or suspension and using a lens particle ink or suspension. An exemplary apparatus comprises a base; at least one first conductor; a plurality of diodes coupled to the at least one first conductor; at least one second conductor coupled to the plurality of diodes; and a plurality of lenses suspended in a polymer deposited or attached over the diodes. The lenses and the suspending polymer have different indices of refraction. In some embodiments, the lenses and diodes are substantially spherical, and have a ratio of mean diameters or lengths between about 10:1 and 2:1. The diodes may be LEDs or photovoltaic diodes, and in some embodiments, have a junction formed at least partially as a hemispherical shell or cap.
    Type: Grant
    Filed: December 8, 2017
    Date of Patent: December 24, 2019
    Assignee: NthDegree Technologies Worldwide Inc
    Inventors: William Johnstone Ray, Mark D. Lowenthal, Neil O. Shotton, Richard A. Blanchard, Mark Allan Lewandowski, Kirk A. Fuller, Donald Odell Frazier
  • Patent number: 10510928
    Abstract: Printed micro-LEDs have a top metal anode electrode that is relatively tall and narrow and a bottom cathode electrode. After the LED ink is cured, the bottom electrodes are in electrical contact with a conductive layer on a substrate. The locations of the LEDs are random. A thin dielectric layer is then printed between the LEDs, and a thin conductive layer, such as a nano-wire layer, is then printed over the dielectric layer to contact the anode electrodes. The top conductive layer over the tall anode electrodes has bumps corresponding with the locations of the LEDs. An omniphobic liquid is then printed which only resides in the “low” areas of the top conductive layer between the bumps. Any optical material is then uniformly printed over the resulting surface. The printed optical material accumulates only on the bump areas by adhesion and surface tension, so is self-aligned with the individual LEDs.
    Type: Grant
    Filed: June 12, 2019
    Date of Patent: December 17, 2019
    Assignee: Nthdegree Technologies Worldwide Inc.
    Inventors: William Johnstone Ray, Richard A. Blanchard
  • Patent number: 10510863
    Abstract: In one embodiment, a power MOSFET vertically conducts current. A bottom electrode may be connected to a positive voltage, and a top electrode may be connected to a low voltage, such as a load connected to ground. A gate and/or a field plate, such as polysilicon, is within a trench. The trench has a tapered oxide layer insulating the polysilicon from the silicon walls. The oxide is much thicker near the bottom of the trench than near the top to increase the breakdown voltage. The tapered oxide is formed by implanting nitrogen into the trench walls to form a tapered nitrogen dopant concentration. This forms a tapered silicon nitride layer after an anneal. The tapered silicon nitride variably inhibits oxide growth in a subsequent oxidation step.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: December 17, 2019
    Assignee: MAXPOWER SEMICONDUCTOR, INC.
    Inventors: Richard A. Blanchard, Mohamed N. Darwish, Jun Zeng