Abstract: An npnp layered switch is modified to have a composite anode structure. Instead of the continuous p-type bottom anode layer of a typical npnp IGTO device, thyristor, or IGBT, the composite anode is formed of a segmented p-type layer with gaps containing n-type semiconductor material. The n-type material forms a majority carrier path between the bottom anode electrode and the n-type collector of the vertical npn bipolar transistor. When a trenched gate is biased high, the majority carrier path is created between the bottom anode electrode and the top cathode electrode. Such a current path operates at very low operating voltages, starting at slightly above 0 volts. Above operating voltages of about 1.0 volts, the npnp layered switch operates normally and uses regenerative bipolar transistor action to conduct a vast majority of the current. The two current paths conduct in parallel.

Abstract: In a vertical power device with trenched insulated gates, there is an npnp layered structure. The vertical gates turn on the device with a suitable gate bias to conduct a current between a top electrode and a bottom electrode. In an example, implanted n+ source regions are formed in the top surface within a p-well. Between some gates, the overlying dielectric is opened up, by etching, to expose distributed p-type contact regions for the p-well. The dielectric is also opened up to expose areas of the n+ source regions. The top electrode metal directly contacts the exposed p-type contact regions and the n+ source regions to provide distributed emitter-to-base short across the cellular array to improve device performance in the presence of transients. The p-contact regions are isolated from the n+ source regions, prior to the deposition of the metal electrode, due to the p-type contact regions not abutting the n+ source regions.

Abstract: Security systems and methods are provided. In one example, a security system includes at least one lock configured to protect one or more items from theft from a fixture, and a strike plate configured to be mounted to the fixture. The lock comprises a plunger pin configured to be moved between a locked state when in engagement with the strike plate and an unlocked state when disengaged from the strike plate, and the lock comprises a cam configured to move the plunger pin between the locked state and the unlocked state. The lock is configured to be moved between a latched position and an unlatched position while the lock is in the unlocked state, the fixture configured to be accessed in the unlatched position, and the strike plate is configured to move relative to the lock to align the lock with the strike plate when the lock is moved from the unlatched position to the latched position.

Abstract: An npnp layered switch is modified to have a composite anode structure. Instead of the continuous p-type bottom anode layer of a typical npnp IGTO device, thyristor, or IGBT, the composite anode is formed of a segmented p-type layer with gaps containing n-type semiconductor material. The n-type material forms a majority carrier path between the bottom anode electrode and the n-type collector of the vertical npn bipolar transistor. When a trenched gate is biased high, the majority carrier path is created between the bottom anode electrode and the top cathode electrode. Such a current path operates at very low operating voltages, starting at slightly above 0 volts. Above operating voltages of about 1.0 volts, the npnp layered switch operates normally and uses regenerative bipolar transistor action to conduct a vast majority of the current. The two current paths conduct in parallel.

Abstract: A sacrificial substrate wafer is provided. A low resistivity etch stop layer is formed on or in the top surface of the wafer. The etch stop layer may be a highly doped, p+ type epitaxially grown layer, or an implanted p+ type boron layer, or an epitaxially grown p+ type SiGe layer. Various epitaxial layers, such as an n? type drift layer, and doped regions are then formed over the etch stop layer to form a vertical power device. The starting wafer is then removed by a combination of mechanical grinding/polishing to leave a thinner layer of the starting wafer. A chemical or plasma etch is then used to remove the remainder of the starting wafer, using the etch stop layer to automatically stop the etching. A bottom metal electrode is then formed on the etch stop layer. The etch stop layer injects hole carriers into the drift layer.

Abstract: After the various regions of a vertical power device are formed in or on the top surface of an n-type wafer, the wafer is thinned, such as by grinding. A drift layer may be n-type, and various n-type regions and p-type regions in the top surface contact a top metal electrode. A blanket dopant implant through the bottom surface of the thinned wafer is performed to form an n? buffer layer and a bottom p+ emitter layer. Energetic particles are injected through the bottom surface to intentionally damage the crystalline structure. A wet etch is performed, which etches the damaged crystal at a much greater rate, so some areas of the n? buffer layer are exposed. The bottom surface is metallized. The areas where the metal contacts the n? buffer layer form cathodes of an anti-parallel diode for conducting reverse voltages, such as voltage spikes from inductive loads.

Abstract: A design technique is disclosed that divides up a cellular power switch into different size segments. Each segment is driven by a different driver circuit. The selection of the combination of segments is made to minimize the combined conduction and switching losses of the power switch. For example, for very light loads, switching losses dominate so only a small segment is activated for driving the load. For medium and high load currents, conduction losses become more significant, so additional segments are activated to minimize the total losses. In one embodiment, the number of cells in the segments is binary weighted, such as 1×, 2×, and 4×, so that there are seven different combinations of segments. The drivers may be configured to achieve the same or different slew rates of the segments, such as to reduce transients. The segments may all be in the same die or a plurality of dies.

Abstract: Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.

Abstract: Merchandise security systems and methods are provided. In one example, a merchandise security system includes a plurality of locks configured to protect one or more items from theft, each of the plurality of locks configured to wirelessly communicate with one or more mobile computing devices. Each of the plurality of locks is configured to establish communication with one or more of the mobile computing devices using a first communication protocol. Each of the plurality of locks is configured to subsequently communicate with one or more of the mobile computing devices using a second communication protocol, different than the first communication protocol, for identifying one or more of the plurality of locks to be unlocked. The one or more of the plurality of locks identified by the one or more mobile computing devices is configured to be unlocked in response to subsequently communicating with the one or more of the plurality of locks using the first communication protocol.

Abstract: A trenched, vertical MOS-gated switch is described that uses only three or four masking steps to fabricate. In one embodiment, one mask is used to form first trenches having a first depth, wherein the first trenches are filled with doped polysilicon to form gates to control the conduction of the switch. A second mask is used to form second trenches having a shallower second depth. The second trenches are filled with the same metal used to form the top source electrode and gate electrode. The metal filling the second trenches electrically contacts a top source layer and a body region. A third mask is used to etch the metal to define the source metal, the gate electrode, and floating rings in a termination region surrounding the active area of the switch. An additional mask may be used to form third trenches in the termination region that are deeper than the first trenches.

Abstract: An insulated gate turn-off (IGTO) device, formed as a die, has a layered structure including a p+ layer (e.g., a substrate), an n? epi layer, a p-well, trenched insulated gate regions formed in the p-well, and n+ regions between the gate regions, so that vertical NPN and PNP transistors are formed. The device may be formed of a matrix of cells or may be interdigitated. To turn the device on, a positive voltage is applied to the gate, referenced to the cathode. The cells further contain a vertical p-channel MOSFET, for rapidly turning the device off. The p-channel MOSFET may be made a depletion mode device by implanting boron ions at an angle into the trenches to create a p-channel. This allows the IGTO device to be turned off with a zero gate voltage while in a latch-up condition, when the device is acting like a thyristor.

Abstract: On a flexible substrate is printed LEDs and a driver circuit containing transistors. The LEDs and transistors are printed microscopic devices contained in an ink. The LEDs are printed in groups and connected in parallel, and the transistors are printed in groups and connected in parallel. Other components, such as resistors and an on/off switch, are also printed to form the driver. A battery and other circuit components may also be printed on the substrate. An overlay is provided over the LEDs to create a desired light pattern. The LEDs and driver may be generic, and the overlay customizes the light pattern for a particular application. The transistors in the driver may be interconnected with a trace pattern to drive the LEDs in a customized manner, such as for an insert in a product package for marketing to a consumer.

Abstract: Layout to reduce current crowding at endpoints. At least one example is a semiconductor device comprising: an emitter region defining an inner boundary in the shape of an obround with parallel sides, and the obround having hemispherical ends each having a radius; a base region having a first end, a second end opposite the first end, and base length, the base region disposed within the obround with the base length parallel to and centered between the parallel sides, the first end spaced apart from the first hemispherical end by a first gap greater than the radius, and the second end spaced apart from the second hemispherical ends by a second gap greater than the radius.

Abstract: A vertical transistor structure in which a recessed field plate trench surrounds multiple adjacent gate electrodes. Thus the specific on-state conductance is increased, since the ratio of recessed field plate area to channel area is reduced. Various versions use two, three, or more distinct gate electrodes within the interior of a single RFP or RSFP trench's layout.

Abstract: Over a flexible substrate are deposited stacked pixel layers including a bottom layer of LEDs forming blue pixels, a middle layer of LEDs forming green pixels, and a top layer of LEDs forming red pixels. Each LED die comprises an LED portion and an integrated transistor portion. Applying a voltage to a control terminal of the transistor portion energizes the LED portion. The pixels are substantially transparent, due to the LEDs being microscopic and the pixel areas being much larger, to allow light from the underlying layers to pass through. The three layers of pixels are aligned so that a combination of a single top red pixel, a single underlying green pixel, and a single underlying blue pixel form a single multi-color pixel. The different layers have transparent column and row lines.

Abstract: In an insulated trench gate device, polysilicon in the trench is etched below the top surface of the trench, leaving a thin gate oxide layer exposed near the top of the trench. An angled implant is conducted that implants dopants through the exposed gate oxide and into the side of the trench. If the implanted dopants are n-type, this technique may be used to extend an n+ source region to be below the top of the polysilicon in the trench. If the implanted dopants are p-type, the dopants may be used to form a p-MOS device that turns on when the polysilicon is biased with a negative voltage. P-MOS and n-MOS devices can be formed in a single cell using this technique, where turning on the n-MOS device turns on a vertical power switch, and turning on the p-MOS device turns off the power switch.

Abstract: Trenches having a gate oxide layer are formed in the surface of a silicon wafer for vertical gates. Conductive doped polysilicon is then deposited in the trenches to form a relatively thin layer of doped polysilicon along the sidewalls. Thus, there is a central cavity surrounded by polysilicon. Next, the cavity is filled in with a much higher conductivity material, such as aluminum, copper, a metal silicide, or other conductor to greatly reduce the overall resistivity of the trenched gates. The thin polysilicon forms an excellent barrier to protect the gate oxide from diffusion from the inner conductor atoms. The inner conductor and the polysilicon conduct the gate voltage in parallel to lower the resistance of the gates, which increases the switching speed of the device. In another embodiment, a metal silicide is used as the first layer, and a metal fills the cavity.

Abstract: A design technique is disclosed that divides up a cellular power switch into different size segments. Each segment is driven by a different driver circuit. The selection of the combination of segments is made to minimize the combined conduction and switching losses of the power switch. For example, for very light loads, switching losses dominate so only a small segment is activated for driving the load. For medium and high load currents, conduction losses become more significant, so additional segments are activated to minimize the total losses. In one embodiment, the number of cells in the segments is binary weighted, such as 1×, 2×, and 4×, so that there are seven different combinations of segments. The drivers may be configured to achieve the same or different slew rates of the segments, such as to reduce transients. The segments may all be in the same die or a plurality of dies.

Abstract: A power device is divided into an active area, an active area perimeter, and a termination region. An array of insulated gates formed in trenches form cells in a p-well body, where n+ source regions are formed in the top surface of the silicon wafer and surround the tops of the trenches. A top cathode electrode contacts the source regions, and an anode electrode is on the bottom of the die. A sufficiently high reverse voltage causes a breakdown current to flow between the anode and cathode electrodes. To ensure that a reverse breakdown voltage current occurs away from the gate oxide and/or the termination region, the active area and the active area perimeter of the p-well are additionally doped with p-type dopants to form deep p+ regions in selected areas that extend below the trenches. The deep p+ regions channel the breakdown current away from active cells and the termination region.

Abstract: Over a flexible substrate are deposited stacked pixel layers including a bottom layer of LEDs forming blue pixels, a middle layer of LEDs forming green pixels, and a top layer of LEDs forming red pixels. Each LED die comprises an LED portion and an integrated transistor portion. Applying a voltage to a control terminal of the transistor portion energizes the LED portion. The pixels are substantially transparent, due to the LEDs being microscopic and the pixel areas being much larger, to allow light from the underlying layers to pass through. The three layers of pixels are aligned so that a combination of a single top red pixel, a single underlying green pixel, and a single underlying blue pixel form a single multi-color pixel. The different layers have transparent column and row lines.