Abstract: A machine learning model for each die for imputing process control parameters at the die. The model is based on wafer sort parametric measurements at multiple test sites across the entire wafer, as well as yield results for the wafer. This allows for a better analysis of outlier spatial patterns leading to improved yield results.

Abstract: A semiconductor image classifier. Convolution functions are applied to modify the wafer images in order to extract key information about the image. The modified images are condensed then processed through a series of pairwise classifiers, each classifier configured to determine that the image is more like one of the pair than the other. Probabilities from each classifier are collected to form a prediction for each image.

Abstract: An improved computing system can use mobility data corresponding to a particular mobile device to identify one or more geographic locations to which the mobile device traveled within a certain period of time. The computing system can use parcel data to identify parcels that are located at any one of the identified geographic locations. The computing system can further use the parcel data to identify a subset of the identified parcels that are listed for sale or rent. If the computing system identifies at least one parcel that the mobile device visited that is available on the market, this may indicate that the user who operates the mobile device may be shopping for a home. In response, the computing system can update information about the user to indicate that the user may be shopping for a home.

Abstract: A template for assigning the most probable root causes for wafer defects. The bin map data for a subject wafer can be compared with bin map data for prior wafers to find wafers with similar issues. A probability can be determined as to whether the same root cause should be applied to the subject wafer, and if so, the wafer can be labeled with that root cause accordingly.

Abstract: A template for assigning the most probable root causes for wafer defects. The bin map data for a subject wafer can be compared with bin map data for prior wafers to find wafers with similar issues. A probability can be determined as to whether the same root cause should be applied to the subject wafer, and if so, the wafer can be labeled with that root cause accordingly.

Abstract: Automatic definition of windows for trace analysis. For each process step, the trace data are aligned to both the start of the process step and the end of the process step, and statistics including rate of change are calculated from both the start of the process step and the end of the process step. Windows are generated based on analysis of the calculated statistics.

Abstract: A predictive model for equipment fail modes. An anomaly is detected in a collection of trace data, then key features are calculated. A search is conducted for the same or similar anomalies having the same key features in a database of past trace data. If the same anomaly occurred before and is in the database, then the type of anomaly, its root cause, and action steps to correct can be retrieved from the database.

Abstract: Enhancement of less dominant patterns for parametric wafer measurements. Dominant patterns are removed from the parametric pattern thereby revealing a less dominant pattern. The less dominant patterns can be used to identify root causes for yield loss that are not visible in the original parametric measurements.

Abstract: Scheme for detection and classification of semiconductor equipment faults. Sensor traces are monitored and processed to separate known abnormal operating conditions from unknown abnormal operating conditions. Feature engineering permits focus on relevant traces for a targeted feature. A machine learning model is built to detect and classify based on an initial classification set of anomalies. The machine learning model is continuously updated as more traces are processed and learned.

Abstract: Semiconductor yield is modeled at the die level to predict die that are susceptible to early lifetime failure (ELF). A first die yield calculation is made from parametric data obtained from wafer testing in a semiconductor manufacturing process. A second die yield calculation is made from die location only. The difference between the first die yield calculation and the second die yield calculation is a prediction delta. Based on an evaluation of the first die yield calculation and the prediction delta, the likelihood of early lifetime failure can be identified and an acceptable level of die loss can be established to remove die from further processing.

Abstract: Wafer quality is determined by modeling equipment history as a sequence of events, then evaluating anomalous results for individual events. Identifying an event that generates bad wafers narrows the list of possible root causes.

Abstract: Enhancement of less dominant patterns for parametric wafer measurements. Dominant patterns are removed from the parametric pattern thereby revealing a less dominant pattern. The less dominant patterns can be used to identify root causes for yield loss that are not visible in the original parametric measurements.

Abstract: A predictive model for equipment fail modes. An anomaly is detected in a collection of trace data, then key features are calculated. A search is conducted for the same or similar anomalies having the same key features in a database of past trace data. If the same anomaly occurred before and is in the database, then the type of anomaly, its root cause, and action steps to correct can be retrieved from the database.

Abstract: Automatic definition of windows for trace analysis. For each process step, the trace data are aligned to both the start of the process step and the end of the process step, and statistics including rate of change are calculated from both the start of the process step and the end of the process step. Windows are generated based on analysis of the calculated statistics.

Abstract: A template for assigning the most probable root causes for wafer defects. The bin map data for a subject wafer can be compared with bin map data for prior wafers to find wafers with similar issues. A probability can be determined as to whether the same root cause should be applied to the subject wafer, and if so, the wafer can be labeled with that root cause accordingly.

Abstract: A semiconductor image classifier. Convolution functions are applied to modify the wafer images in order to extract key information about the image. The modified images are condensed then processed through a series of pairwise classifiers, each classifier configured to determine that the image is more like one of the pair than the other. Probabilities from each classifier are collected to form a prediction for each image.

Abstract: Semiconductor yield is modeled at the die level to predict die that are susceptible to early lifetime failure (ELF). A first die yield calculation is made from parametric data obtained from wafer testing in a semiconductor manufacturing process. A second die yield calculation is made from die location only. The difference between the first die yield calculation and the second die yield calculation is a prediction delta. Based on an evaluation of the first die yield calculation and the prediction delta, the likelihood of early lifetime failure can be identified and an acceptable level of die loss can be established to remove die from further processing.

Abstract: Classifying wafers using Collaborative Learning. An initial wafer classification is determined by a rule-based model. A predicted wafer classification is determined by a machine learning model. Multiple users can manually review the classifications to confirm or modify, or to add user classifications. All of the classifications are input to the machine learning model to continuously update its scheme for detection and classification.

Abstract: A sequence of models accumulates r-squared values for an increasing number of variables in order to quantify the importance of each variable to the prediction of a targeted yield or parametric response.

Abstract: A machine learning model for each die for imputing process control parameters at the die. The model is based on wafer sort parametric measurements at multiple test sites across the entire wafer, as well as yield results for the wafer. This allows for a better analysis of outlier spatial patterns leading to improved yield results.