Abstract: A jitter/wander reduction mechanism monitors the ratio of pulse stuffing, to detect whenever the pulse stuffing ratio is proximate a prescribed undesirable ratio of stuffs per stuffing opportunity, which causes the wander to be a large number of unit intervals. A stuffing pulse accumulator-controlled frequency shift control circuit monitors the signal produced by a multiplexer (and demultiplexer for full duplex mode) control logic circuit and incrementally adjusts, as necessary, the frequency of a synchronized clock signal input to the multiplexer (and demultiplexer). The magnitude of the incremental frequency shift is sufficient to drive the synchronized clock away from the frequency associated with the undesired stuff ratio to a frequency that is sufficiently separated from the undesired value to produce a stuffing ratio other than the undesired value and reduce the jitter/wander.

Abstract: A jitter/wander reduction circuit is provided for a desynchronizer deriving an output clock signal from an independent clock signal and phase adjustment signals. Phase adjustment signals relate to a deviation of the independent clock signal from an input clock signal. The circuit includes a frequency offset estimation circuit receiving phase adjustment signals and providing a frequency offset estimation signal. A phase controller receives the frequency offset estimation signal, provides a feedback signal to the frequency offset estimation circuit, and provides a phase difference signal. A clock generator circuit receives the independent clock signal and the phase difference signal. The independent clock signal is adjusted based on the phase difference signal to provide an output clock signal.

Abstract: The need to employ costly precision components to reduce non-linearities in the signal processing path of noise reduction circuitry such as an echo canceler and decision feedback equalizer is successfully addressed by a transversal filter which is capable of effectively tracking for non-linearities in system components that manifest themselves as added noise introduced into the signal propagation path. This non-linear tracking capability is attained by employing cascaded sets of weighting coefficient and scaling factor multiplying stages. The first set of weighting coefficients effectively modifies the contents of each of the transmitted symbol samples in the transversal filter delay line to produce respective sets of `partial sums` associated with the respective data symbols employed in the data modulation scheme. The second, cascaded set of `scaling` coefficients or factors is employed to scale selected ones of the sets of the partial sums.

Abstract: The need to employ costly precision components to reduce non-linearities in the signal processing path of noise reduction circuitry such as an echo canceler and decision feedback equalizer is successfully addressed by a transversal filter which is capable of effectively tracking for non-linearities in system components that manifest themselves as added noise introduced into the signal propagation path. This non-linear tracking capability is attained by employing cascaded sets of weighting coefficient and scaling factor multiplying stages. The first set of weighting coefficients effectively modifies the contents of each of the transmitted symbol samples in the transversal filter delay line to produce respective sets of `partial sums` associated with the respective data symbols employed in the data modulation scheme. The second, cascaded set of `scaling` coefficients or factors is employed to scale selected ones of the sets of the partial sums.

Abstract: In a digital data receiver, it is desirable to use the equalized data for deriving time synchronization information. This invention minimizes timing contention between an equalizer operating at a T/2 rate and a timing recovery circuit which utilizes the output of the equalizer. An interpolator interpolates T1 and T2 data samples from the equalizer and provides data signals R and S equally spaced relative to the peak baud amplitude which can be easily processed by the timing recovery circuit.