Abstract: A system and method for failure recovery in a multiple processing node system are described herein. Each node can be adapted to store a backup copy of its database portion and/or results to disk storage or memory of at least one other node. In the event of a failure of a node, the replacement node can be adapted to transfer or copy the backup copy of the database portion of the failed node from the failed node's neighbors to the replacement node's disk storage or memory in between database operations. Before the transfer or copy of the backup copy is completed, the replacement node can be adapted to perform database operations in part on the portion of the backup copy the replacement node has already received and in part on the backup copy stored at the neighboring node(s).

Abstract: A method for distributing and sorting data among a plurality of nodes is describe herein. After receiving a portion of a data set (e.g., a database), each node sorts its portion and estimates a partitioning of the sorted dataset among the nodes based in part on its own sorted data portion. Each node then provides a representation of its estimated partition to a master node. The master node, using the provided estimated partitions, determines a tentative partitioning and submits the tentative partitioning to each node. Each node then determines the effect the tentative partitioning using its data portion. If the effect is acceptable for each node, the tentative partitioning plan is used to partition the data. Otherwise, the tentative partitioning plan is repeatedly revised by the master node and considered by the nodes having data portions until an acceptable or optimum partitioning is determined.

Abstract: A system and method for configuring a plurality of processing nodes into a parallel-processing database system are described herein. Each of a plurality of processing nodes connected by a network receive software and one or more configuration files related to the intended function of the processing node. The software may include homogeneous agent software, one or more library dynamic-link libraries (DLL), and the like. The configuration file is used to configure the homogeneous agent to operate as the intended node in a global-results processing matrix, a general-purpose query processing matrix, or a index-base query processing matrix. Another node or nodes may be configured to convert query-based programming code to intermediary source code in a common programming language and then compile the intermediary source code into a dynamic link library (DLL) or other type of executable.

Abstract: A system and method for scheduling database operations to one or more databases in a parallel-processing database system are described herein. After a query server generates a dynamic-link library (DLL) or other executable representative of one or more database operations to a database, the query server notifies a scheduling services module of the generation of the DLL and submits the DLL to a query agent. The query agent notifies the scheduling services module of its receipt of the DLL. Based on any of a variety of considerations, the scheduling services module schedules a time of execution for the DLL by one or more processing matrices that store the database. At the scheduled time, the scheduling services module directs the query agent to submit the DLL to the indicated processing matrices. The scheduling services module also can be adapted to monitor the execution of previously submitted DLLs by one or more processing matrices and adjust the scheduled times of execution for subsequent DLLs accordingly.

Abstract: Extrusion processability of non-fluorinated melt-processable polymers is improved by introducing a fluoropolymer process aid by means whereby the weight average particle size of the fluoropolymer is greater than 2 microns as it reaches the extruder die entrance.

Abstract: Extrusion processability of non-fluorinated melt-processable polymers is improved by introducing a fluoropolymer process aid by means whereby the weight average particle size of the fluoropolymer is greater than 2 microns as it reaches the extruder die entrance.

Abstract: A method for monitoring an etch process of a substrate that includes receiving a first signal having a first wavelength, deriving a second signal based on the first signal and combining the first signal with the second signal to produce a composite signal having a composite wavelength less than the first wavelength. The method further includes identifying one or more inflection points of the composite signal and determining an etch rate of an etch process by evaluating the inflection points and elapsed time between the inflection points.

Abstract: Extrusion processability of non-fluorinated melt-processable polymers is improved by introducing a fluoropolymer process aid by means whereby the weight average particle size of the fluoropolymer is greater than 2 microns as it reaches the extruder die entrance.

Abstract: A method of fabricating a CMOS transistor to construct shallow drain extenders (30) using a replacement gate design. The method involves forming epitaxial layers (30) and (220) the will later function as shallow drain extensions. The etching of the replacement gate (220) and the formation of inner sidewalls (90) serve to define the transistor gate length.

Abstract: A semiconductor device having high and low voltage transistors on the same chip. High voltage NMOS transistor 76 comprises a polysilicon gate 40 doped at first dopant level. Low voltage NMOS transistor comprises a polysilicon gate 44 doped at a second dopant level. The second dopant level is higher than the first. High voltage PMOS transistor 84 comprises a polysilicon gate 48 doped at a third dopant level. Low voltage PMOS transistor comprises a polysilicon gate 52 doped at a fourth dopant level. The fourth dopant level is higher than the third.

Abstract: The invention relates to a device for cutting material such as metal rod. The device comprises a diaphragm type air brake chamber having a wedge mounted to an output shaft of the chamber, a cutting assembly mounted to the air brake chamber, the assembly comprising two pivotally mounted cutting members with opposed blades with the members biased to maintain an opening between the blades, and a handle for gripping the device rearwardly of the cutting assembly. The device is configured so that on actuation of the air brake chamber, the wedge is driven between ends of the cutting members distal the blades to cause the blades to pivot towards each other.

Abstract: A transistor (100) having a strip channel or channels (108) in which the current flow in is the lateral direction between source (110) and drain (112). The gate (116) is located on the sidewalls and, if desired, the top of the strip channel (108). In a preferred embodiment of the invention, a disposable gate process is used that allows the source (110) and drain (112) regions to be self-aligned to the gate (116).

Abstract: A counter-doped epitaxial silicon (doped opposite to the substrate type) is used to form the buried layer in a CMOS transistor, while maintaining an abrupt channel profile. Shallow source/drain junctions with abrupt source/drain profiles may be formed using raised (or elevated) source/drain design. The invention encompasses a transistor structure including a doped silicon substrate, and an oppositely-doped epitaxial silicon layer formed on the substrate. A gate is formed on the epitaxial layer, the gate defining a channel region in the epitaxial layer underneath the gate. A layer is formed on the epitaxial silicon layer on opposing sides of, and is electrically isolated from, the gate.

Abstract: System for data input and storage and for correlation of such data against group data contained in a linked database. The data is input via a series of hierarchical menus, which menus may include sub-menus and fields that enable a user to directly input data for storage into the database. Data regarding an individual may be entered into the database directly by the individual using the hierarchical menu system.

Abstract: A counter-doped epitaxial silicon (doped opposite to the substrate type) is used to form the buried layer in a CMOS transistor, while maintaining an abrupt channel profile. Shallow source/drain junctions with abrupt source/drain profiles may be formed using raised (or elevated) source/drain design. The invention encompasses a transistor structure including a doped silicon substrate, and an oppositely-doped epitaxial silicon layer formed on the substrate. A gate is formed on the epitaxial layer, the gate defining a channel region in the epitaxial layer underneath the gate. A layer is formed on the epitaxial silicon layer on opposing sides of, and is electrically isolated from, the gate.

Abstract: A transistor (100) having a strip channel or channels (108) in which the current flow in is the lateral direction between source (110) and drain (112). The gate (116) is located on the sidewalls and, if desired, the top of the strip channel (108). In a preferred embodiment of the invention, a disposable gate process is used that allows the source (110) and drain (112) regions to be self-aligned to the gate (116).

Abstract: A method for forming a MOSFET transistor (100) using a disposable gate (120). A disposable gate (120) having at least two materials (122,124) that may be etched selectively with respect to each other is formed on a semiconductor substrate (102). Source/drain regions (104) are then formed adjacent the disposable gate. The source/drain regions may, for example, include raised source/drain regions (106). An insulator layer (114) is then deposited over the structure and then a portion of the insulator layer (114) over the disposable gate (120) is removed (e.g., using CMP or an etch-back). The composition of the insulator layer (114) is chosen such that the top layer (124) of the disposable gate (120) may be removed selectively with respect to the insulator layer (114). The disposable gate (120) is then removed and a channel implant may be performed that is self-aligned and only in the channel region. The gate dielectric (110) and gate electrode (112) are then formed.

Abstract: A kernel for enforcing a hierarchical invocation structure prevents upcalls by executing kernel operations during each invocation of code unit of application by another code unit. Kernel operations determine the priority of the invoking unit of code based on the hierarchy of the invocation structure. Only invocations by either lower priority units, or the unit itself are allowed. Once invoked, the kernel operates to establish a priority for the invoked task. The kernel provides various event mechanisms to provide for priority based preemption concurrently with the enforced invocation structure, thus allowing the handling of asynchronous events in a multitasking environment. The event mechanisms allow a unit of code to signal the occurrence of a condition, which may be captured by other code units. The kernel determines the proper code unit for responding to the condition, and employs scope rules to further define the handling operation.

Abstract: A process for forming high voltage and low voltage transistors on the same substrates includes first forming a poly gate (16) over layer gate oxide (10) on a substrate (12). An LDD implant is then performed, followed by the formation of a nitride cap (30) over the gate (16). The cap (30) is not disposed over gate electrodes associated with low voltage transistors. Thereafter, the source/drain implant is performed which forms source/drain regions (40) and (42). The cap (30) prevents the introduction of dopants into the gate electrode (16) during the source/drain implant step. This effectively increases the gate oxide width due to a larger depletion region at the oxide/polysilicon gate boundary as compared to the low voltage transistors with the higher dopant levels and the gate electrode.

Abstract: A method is provided for increasing the electrical activation of dopants in a semiconductor device using rapid thermal processing (RTP). An aspect of the invention includes forming a gate on a semiconductor body (12), such as a substrate (14), and implanting a dopant (28) into the semiconductor body (12) proximate the gate. The dopant (28) is partially activated using a furnace. The dopant (28) is further activated using RTP. The activation of the dopant (28) through RTP in addition to the furnace annealing allows almost complete activation of the dopant while maintaining acceptable channel depths.