Abstract: A processor-implemented method for simultaneously tracking one or more objects includes receiving, via a dynamical system with a set of sensors, a first set of unlabeled measurements from one or more objects. Each of the measurements is a function of time. A set of candidate tracks is determined for the one or more objects. Probabilities of each of the first set of unlabeled measurements being assigned to each of the set of candidate tracks are computed. A track from the set of candidate tracks is determined for each of the one or more objects based on a joint probability distribution of track attributes and the probabilistic assignment of each of the first set of unlabeled measurements to each of the set of candidate tracks.

Abstract: A system for allocation of one or more data structures used in a program across a number of processing units takes into account a memory access pattern of the data structure, and the amount of total memory available for duplication across the several processing units. Using these parameters duplication factors are determined for the one or more data structures such that the cost of remote communication is minimized when the data structures are duplicated according to the respective duplication factors while allowing parallel execution of the program.

Abstract: In a system for automatic generation of event-driven, tuple-space based programs from a sequential specification, a hierarchical mapping solution can target different runtimes relying on event-driven tasks (EDTs). The solution uses loop types to encode short, transitive relations among EDTs that can be evaluated efficiently at runtime. Specifically, permutable loops translate immediately into conservative point-to-point synchronizations of distance one. A runtime-agnostic which can be used to target the transformed code to different runtimes.

Abstract: A multiresolution parser (MRP) can selectively extract one or more information units from a dataset based on the available processing capacity and/or the arrival rate of the dataset. Should any of these parameters change, the MRP can adaptively change the information units to be extracted such that the benefit or value of the extracted information is maximized while minimizing the cost of extraction. This tradeoff is facilitated, at least in part, by an analysis of the spectral energy of the datasets expected to be processed by the MRP. The MRP can also determine its state after a processing iteration and use that state information in subsequent iterations to minimize the required computations in such subsequent iterations, so as to improve processing efficiency.

Abstract: A system for determining the physical path of an object can map several candidate paths to a suitable path space that can be explored using a convex optimization technique. The optimization technique may take advantage of the typical sparsity of the path space and can identify a likely physical path using a function of sensor observation as constraints. A track of an object can also be determined using a track model and a convex optimization technique.

Abstract: A processor-implemented method includes approximating an optimization problem for training an artificial neural network as a nested polynomial optimization problem. The method also includes dividing the nested polynomial optimization problem into a sequence of sub-problems. The method further includes hierarchically solving the sequence of sub-problems to train the artificial neural network.

Abstract: A system for extracting latent information from data includes obtaining or generating components of the data, where the data components include scores indicating how the component relates to the data. Memory is allocated for the components and the components are stored in the allocated memory. The components are then transformed into documents using a suitable transformation function, and the documents are analyzed using natural language processing, to extract latent information contained in the data.

Abstract: In a network system, an application receiving packets can consume one or more packets in two or more stages, where the second and the later stages can selectively consume some but not all of the packets consumed by the preceding stage. Packets are transferred between two consecutive stages, called producer and consumer, via a fixed-size storage. Both the producer and the consumer can access the storage without locking it and, to facilitate selective consumption of the packets by the consumer, the consumer can transition between awake and sleep modes, where the packets are consumed in the awake mode only. The producer may also switch between awake and sleep modes. Lockless access is made possible by controlling the operation of the storage by the producer and the consumer both according to the mode of the consumer, which is communicated via a shared memory location.

Abstract: In a system for storing in memory a tensor that includes at least three modes, elements of the tensor are stored in a mode-based order for improving locality of references when the elements are accessed during an operation on the tensor. To facilitate efficient data reuse in a tensor transform that includes several iterations, on a tensor that includes at least three modes, a system performs a first iteration that includes a first operation on the tensor to obtain a first intermediate result, and the first intermediate result includes a first intermediate-tensor. The first intermediate result is stored in memory, and a second iteration is performed in which a second operation on the first intermediate result accessed from the memory is performed, so as to avoid a third operation, that would be required if the first intermediate result were not accessed from the memory.

Abstract: In a sequence of major computational steps or in an iterative computation, a stencil amplifier can increase the number of data elements accessed from one or more data structures in a single major step or iteration, thereby decreasing the total number of computations and/or communication operations in the overall sequence or the iterative computation. Stencil amplification, which can be optimized according to a specified parameter such as compile time, rune time, code size, etc., can improve the performance of a computing system executing the sequence or the iterative computation in terms of run time, memory load, energy consumption, etc. The stencil amplifier typically determines boundaries, to avoid erroneously accessing data elements not present in the one or more data structures.

Abstract: A technique is described for quantifying a change in a system parameter in response to a perturbation of another system parameter. The technique identifies a region of influence of the perturbation and limits the propagation of the perturbation to the identified region.

Abstract: A system for performing tensor decomposition in a selective expansive and/or recursive manner, a tensor is decomposed into a specified number of components, and one or more tensor components are selected for further decomposition. For each selected component, the significant elements thereof are identified, and using the indices of the significant elements a sub-tensor is formed. In a subsequent iteration, each sub-tensor is decomposed into a respective specified number of components. Additional sub-tensors corresponding to the components generated in the subsequent iteration are formed, and these additional sub-tensors may be decomposed further in yet another iteration, until no additional components are selected. The mode of a sub-tensor can be decreased or increased prior to decomposition thereof. Components likely to reveal information about the data stored in the tensor can be selected for decomposition.

Abstract: A processor-implemented method includes receiving, as input, an array of values characterizing a polynomial feasibility problem representing a physical system for solving a computational problem. The method also includes reducing dimensions of the polynomial feasibility problem by transforming the polynomial feasibility problem into a high-dimensional linear feasibility problem and a non-linear feasibility problem. The method further includes solving the high-dimensional linear feasibility problem to obtain a first set of interim solutions. The method includes solving the non-linear feasibility problem based on the first set of interim solutions to obtain a result of the non-linear feasibility problem. The method also includes outputting parameters characterizing the physical system, with a ground state corresponding to an output solution of the computational problem based on the result obtained from solving the non-linear feasibility problem.

Abstract: A processor-implemented method includes receiving as input, a global polynomial optimization problem that approximates a training problem of a neural network. The method also includes relaxing the global polynomial optimization problem including polynomial constraints with multiple semi-definite programs. The method further includes solving the semi-definite programs based on a pre-defined structure and outputting a solution indicating a location of a global optimum of the optimization problem. The method includes performing inference with the neural network based on the solution.

Abstract: A compilation system using an energy model based on a set of generic and practical hardware and software parameters is presented. The model can represent the major trends in energy consumption spanning potential hardware configurations using only parameters available at compilation time. Experimental verification indicates that the model is nimble yet sufficiently precise, allowing efficient selection of one or more parameters of a target computing system so as to minimize power/energy consumption of a program while achieving other performance related goals. A voltage and/or frequency optimization and selection is presented which can determine an efficient dynamic hardware configuration schedule at compilation time. In various embodiments, the configuration schedule is chosen based on its predicted effect on energy consumption. A concurrency throttling technique based on the energy model can exploit the power-gating features exposed by the target computing system to increase the energy efficiency of programs.

Abstract: Methods, apparatus and computer software product for optimization of data transfer between two memories includes determining access to master data stored in one memory and/or to local data stored in another memory such that either or both of the size of total data transferred and the number of data transfers required to transfer the total data can be minimized. The master and/or local accesses are based on, at least in part, respective structures of the master and local data.

Abstract: A technique is described for quantifying the effect of a perturbation on a property of a network link or flow, and to add a new flow, reroute an existing flow, or to reshape a flow, based on a quantitative estimation of the perturbation.

Abstract: A multiresolution parser (MRP) can selectively extract one or more information units from a dataset based on the available processing capacity and/or the arrival rate of the dataset. Should any of these parameters change, the MRP can adaptively change the information units to be extracted such that the benefit or value of the extracted information is maximized while minimizing the cost of extraction. This tradeoff is facilitated, at least in part, by an analysis of the spectral energy of the datasets expected to be processed by the MRP. The MRP can also determine its state after a processing iteration and use that state information in subsequent iterations to minimize the required computations in such subsequent iterations, so as to improve processing efficiency.

Abstract: A technique is described for quantifying a change in a system parameter in response to a perturbation of another system parameter by identifying a region of influence of the perturbation and by limiting the propagation of the perturbation to the identified region.

Abstract: A system for allocation of one or more data structures used in a program across a number of processing units takes into account a memory access pattern of the data structure, and the amount of total memory available for duplication across the several processing units. Using these parameters duplication factors are determined for the one or more data structures such that the cost of remote communication is minimized when the data structures are duplicated according to the respective duplication factors while allowing parallel execution of the program.