Patents by Inventor Richard A. Lethin

Richard A. Lethin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220057949
    Abstract: A system for allocation of one or more data structures used in a program across a number of processing units takes into account a memory access pattern of the data structure, and the amount of total memory available for duplication across the several processing units. Using these parameters duplication factors are determined for the one or more data structures such that the cost of remote communication is minimized when the data structures are duplicated according to the respective duplication factors while allowing parallel execution of the program.
    Type: Application
    Filed: June 24, 2021
    Publication date: February 24, 2022
    Inventors: Muthu Manikandan Baskaran, Thomas Henretty, Ann Johnson, Athanasios Konstantinidis, M. H. Langston, Janice O. Mcmahon, Benoit J. Meister, Paul D. Mountcastle, Aale Naqvi, Benoit Pradelle, Tahina Ramananandro, Sanket Tavarageri, Richard A. Lethin
  • Publication number: 20220060426
    Abstract: In a network system, an application receiving packets can consume one or more packets in two or more stages, where the second and the later stages can selectively consume some but not all of the packets consumed by the preceding stage. Packets are transferred between two consecutive stages, called producer and consumer, via a fixed-size storage. Both the producer and the consumer can access the storage without locking it and, to facilitate selective consumption of the packets by the consumer, the consumer can transition between awake and sleep modes, where the packets are consumed in the awake mode only. The producer may also switch between awake and sleep modes. Lockless access is made possible by controlling the operation of the storage by the producer and the consumer both according to the mode of the consumer, which is communicated via a shared memory location.
    Type: Application
    Filed: May 10, 2021
    Publication date: February 24, 2022
    Inventors: Jordi Ros-Giralt, Alan Commike, Peter Cullen, Richard A. Lethin
  • Publication number: 20220043827
    Abstract: A system for extracting latent information from data includes obtaining or generating components of the data, where the data components include scores indicating how the component relates to the data. Memory is allocated for the components and the components are stored in the allocated memory. The components are then transformed into documents using a suitable transformation function, and the documents are analyzed using natural language processing, to extract latent information contained in the data.
    Type: Application
    Filed: July 8, 2021
    Publication date: February 10, 2022
    Inventors: James Ezick, Thomas Henretty, Richard A. Lethin
  • Patent number: 11233803
    Abstract: A multiresolution parser (MRP) can selectively extract one or more information units from a dataset based on the available processing capacity and/or the arrival rate of the dataset. Should any of these parameters change, the MRP can adaptively change the information units to be extracted such that the benefit or value of the extracted information is maximized while minimizing the cost of extraction. This tradeoff is facilitated, at least in part, by an analysis of the spectral energy of the datasets expected to be processed by the MRP. The MRP can also determine its state after a processing iteration and use that state information in subsequent iterations to minimize the required computations in such subsequent iterations, so as to improve processing efficiency.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: January 25, 2022
    Assignee: Reservoir Labs, Inc.
    Inventors: Jordi Ros-Giralt, Alan Commike, Richard A. Lethin
  • Publication number: 20220004425
    Abstract: In a system for automatic generation of event-driven, tuple-space based programs from a sequential specification, a hierarchical mapping solution can target different runtimes relying on event-driven tasks (EDTs). The solution uses loop types to encode short, transitive relations among EDTs that can be evaluated efficiently at runtime. Specifically, permutable loops translate immediately into conservative point-to-point synchronizations of distance one. A runtime-agnostic which can be used to target the transformed code to different runtimes.
    Type: Application
    Filed: February 14, 2020
    Publication date: January 6, 2022
    Inventors: Muthu M. Baskaran, Thomas Henretty, M. H. Langston, Richard A. Lethin, Benoit J. Meister, Nicolas T. Vasilache, David E. Wohlford
  • Patent number: 11200035
    Abstract: Methods, apparatus and computer software product for source code optimization are provided. In an exemplary embodiment, a first custom computing apparatus is used to optimize the execution of source code on a second computing apparatus. In this embodiment, the first custom computing apparatus contains a memory, a storage medium and at least one processor with at least one multi-stage execution unit. The second computing apparatus contains at least one local memory unit that allows for data reuse opportunities. The first custom computing apparatus optimizes the code for reduced communication execution on the second computing apparatus.
    Type: Grant
    Filed: November 27, 2017
    Date of Patent: December 14, 2021
    Assignee: Reservoir Labs, Inc.
    Inventors: Muthu M. Baskaran, Richard A. Lethin, Benoit J. Meister, Nicolas T. Vasilache
  • Publication number: 20210294876
    Abstract: A system for performing tensor decomposition in a selective expansive and/or recursive manner, a tensor is decomposed into a specified number of components, and one or more tensor components are selected for further decomposition. For each selected component, the significant elements thereof are identified, and using the indices of the significant elements a sub-tensor is formed. In a subsequent iteration, each sub-tensor is decomposed into a respective specified number of components. Additional sub-tensors corresponding to the components generated in the subsequent iteration are formed, and these additional sub-tensors may be decomposed further in yet another iteration, until no additional components are selected. The mode of a sub-tensor can be decreased or increased prior to decomposition thereof. Components likely to reveal information about the data stored in the tensor can be selected for decomposition.
    Type: Application
    Filed: November 2, 2020
    Publication date: September 23, 2021
    Inventors: Muthu Manikandan Baskaran, David Bruns-Smith, James Ezick, Richard A. Lethin
  • Publication number: 20210255891
    Abstract: In a system for automatic generation of event-driven, tuple-space based programs from a sequential specification, a hierarchical mapping solution can target different runtimes relying on event-driven tasks (EDTs). The solution uses loop types to encode short, transitive relations among EDTs that can be evaluated efficiently at runtime. Specifically, permutable loops translate immediately into conservative point-to-point synchronizations of distance one. A runtime-agnostic which can be used to target the transformed code to different runtimes.
    Type: Application
    Filed: February 14, 2020
    Publication date: August 19, 2021
    Inventors: Thomas Henretty, Richard A. Lethin, Benoit J. Meister, Nicolas T. Vasilache, David E. Wohlford
  • Patent number: 11074269
    Abstract: A system for extracting latent information from data includes obtaining or generating components of the data, where the data components include scores indicating how the component relates to the data. Memory is allocated for the components and the components are stored in the allocated memory. The components are then transformed into documents using a suitable transformation function, and the documents are analyzed using natural language processing, to extract latent information contained in the data.
    Type: Grant
    Filed: January 10, 2019
    Date of Patent: July 27, 2021
    Assignee: Reservoir Labs, Inc.
    Inventors: James Ezick, Thomas Henretty, Richard A. Lethin
  • Patent number: 11068178
    Abstract: A system for allocation of one or more data structures used in a program across a number of processing units takes into account a memory access pattern of the data structure, and the amount of total memory available for duplication across the several processing units. Using these parameters duplication factors are determined for the one or more data structures such that the cost of remote communication is minimized when the data structures are duplicated according to the respective duplication factors while allowing parallel execution of the program.
    Type: Grant
    Filed: December 2, 2019
    Date of Patent: July 20, 2021
    Assignee: Reservoir Labs, Inc.
    Inventors: Muthu Manikandan Baskaran, Thomas Henretty, Ann Johnson, Athanasios Konstantinidis, M. H. Langston, Janice O. Mcmahon, Benoit J. Meister, Paul D. Mountcastle, Aale Naqvi, Benoit Pradelle, Tahina Ramananandro, Sanket Tavarageri, Richard A. Lethin
  • Publication number: 20210173623
    Abstract: In a sequence of major computational steps or in an iterative computation, a stencil amplifier can increase the number of data elements accessed from one or more data structures in a single major step or iteration, thereby decreasing the total number of computations and/or communication operations in the overall sequence or the iterative computation. Stencil amplification, which can be optimized according to a specified parameter such as compile time, rune time, code size, etc., can improve the performance of a computing system executing the sequence or the iterative computation in terms of run time, memory load, energy consumption, etc. The stencil amplifier typically determines boundaries, to avoid erroneously accessing data elements not present in the one or more data structures.
    Type: Application
    Filed: July 13, 2020
    Publication date: June 10, 2021
    Inventors: Thomas Henretty, Richard A. Lethin, Benoit J. Meister
  • Patent number: 11005772
    Abstract: In a network system, an application receiving packets can consume one or more packets in two or more stages, where the second and the later stages can selectively consume some but not all of the packets consumed by the preceding stage. Packets are transferred between two consecutive stages, called producer and consumer, via a fixed-size storage. Both the producer and the consumer can access the storage without locking it and, to facilitate selective consumption of the packets by the consumer, the consumer can transition between awake and sleep modes, where the packets are consumed in the awake mode only. The producer may also switch between awake and sleep modes. Lockless access is made possible by controlling the operation of the storage by the producer and the consumer both according to the mode of the consumer, which is communicated via a shared memory location.
    Type: Grant
    Filed: November 13, 2018
    Date of Patent: May 11, 2021
    Assignee: Reservoir Labs, Inc.
    Inventors: Jordi Ros-Giralt, Alan Commike, Peter Cullen, Richard A. Lethin
  • Patent number: 10936569
    Abstract: In a system for storing in memory a tensor that includes at least three modes, elements of the tensor are stored in a mode-based order for improving locality of references when the elements are accessed during an operation on the tensor. To facilitate efficient data reuse in a tensor transform that includes several iterations, on a tensor that includes at least three modes, a system performs a first iteration that includes a first operation on the tensor to obtain a first intermediate result, and the first intermediate result includes a first intermediate-tensor. The first intermediate result is stored in memory, and a second iteration is performed in which a second operation on the first intermediate result accessed from the memory is performed, so as to avoid a third operation, that would be required if the first intermediate result were not accessed from the memory.
    Type: Grant
    Filed: May 20, 2013
    Date of Patent: March 2, 2021
    Assignee: Reservoir Labs, Inc.
    Inventors: Muthu Manikandan Baskaran, Richard A. Lethin, Benoit J. Meister, Nicolas T. Vasilache
  • Publication number: 20200393980
    Abstract: A compilation system using an energy model based on a set of generic and practical hardware and software parameters is presented. The model can represent the major trends in energy consumption spanning potential hardware configurations using only parameters available at compilation time. Experimental verification indicates that the model is nimble yet sufficiently precise, allowing efficient selection of one or more parameters of a target computing system so as to minimize power/energy consumption of a program while achieving other performance related goals. A voltage and/or frequency optimization and selection is presented which can determine an efficient dynamic hardware configuration schedule at compilation time. In various embodiments, the configuration schedule is chosen based on its predicted effect on energy consumption. A concurrency throttling technique based on the energy model can exploit the power-gating features exposed by the target computing system to increase the energy efficiency of programs.
    Type: Application
    Filed: January 17, 2020
    Publication date: December 17, 2020
    Inventors: Thomas Henretty, Ann Johnson, Athanasios Konstantinidis, Janice O. Mcmahon, Benoit J. Meister, Paul D. Mountcastle, Aale Naqvi, Benoit Pradelle, Tahina Ramananandro, Sanket Tavarageri, Richard A. Lethin
  • Patent number: 10824693
    Abstract: A system for performing tensor decomposition in a selective expansive and/or recursive manner, a tensor is decomposed into a specified number of components, and one or more tensor components are selected for further decomposition. For each selected component, the significant elements thereof are identified, and using the indices of the significant elements a sub-tensor is formed. In a subsequent iteration, each sub-tensor is decomposed into a respective specified number of components. Additional sub-tensors corresponding to the components generated in the subsequent iteration are formed, and these additional sub-tensors may be decomposed further in yet another iteration, until no additional components are selected. The mode of a sub-tensor can be decreased or increased prior to decomposition thereof. Components likely to reveal information about the data stored in the tensor can be selected for decomposition.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: November 3, 2020
    Assignee: Reservoir Labs, Inc.
    Inventors: Muthu M. Baskaran, David Bruns-Smith, James Ezick, Richard A. Lethin
  • Publication number: 20200284896
    Abstract: A system for determining the physical path of an object can map several candidate paths to a suitable path space that can be explored using a convex optimization technique. The optimization technique may take advantage of the typical sparsity of the path space and can identify a likely physical path using a function of sensor observation as constraints. A track of an object can also be determined using a track model and a convex optimization technique.
    Type: Application
    Filed: October 15, 2019
    Publication date: September 10, 2020
    Inventors: Thomas Henretty, Ann Johnson, Athanasios Konstantinidis, Janice O. Mcmahon, Benoit J. Meister, Paul D. Mountcastle, Aale Naqvi, Benoit Pradelle, Tahina Ramananandro, Sanket Tavarageri, Richard A. Lethin
  • Publication number: 20200278847
    Abstract: Methods, apparatus and computer software product for optimization of data transfer between two memories includes determining access to master data stored in one memory and/or to local data stored in another memory such that either or both of the size of total data transferred and the number of data transfers required to transfer the total data can be minimized. The master and/or local accesses are based on, at least in part, respective structures of the master and local data.
    Type: Application
    Filed: May 18, 2020
    Publication date: September 3, 2020
    Inventors: Richard A. Lethin, Allen K. Leung, Benoit J. Meister, David E. Wohlford
  • Publication number: 20200249855
    Abstract: A system for allocation of one or more data structures used in a program across a number of processing units takes into account a memory access pattern of the data structure, and the amount of total memory available for duplication across the several processing units. Using these parameters duplication factors are determined for the one or more data structures such that the cost of remote communication is minimized when the data structures are duplicated according to the respective duplication factors while allowing parallel execution of the program.
    Type: Application
    Filed: December 2, 2019
    Publication date: August 6, 2020
    Inventors: Thomas Henretty, Ann Johnson, Athanasios Konstantinidis, Janice O. Mcmahon, Benoit J. Meister, Paul D. Mountcastle, Aale Naqvi, Benoit Pradelle, Tahina Ramananandro, Sanket Tavarageri, Richard A. Lethin
  • Patent number: 10713022
    Abstract: In a sequence of major computational steps or in an iterative computation, a stencil amplifier can increase the number of data elements accessed from one or more data structures in a single major step or iteration, thereby decreasing the total number of computations and/or communication operations in the overall sequence or the iterative computation. Stencil amplification, which can be optimized according to a specified parameter such as compile time, run time, code size, etc., can improve the performance of a computing system executing the sequence or the iterative computation in terms of run time, memory load, energy consumption, etc. The stencil amplifier typically determines boundaries, to avoid erroneously accessing data elements not present in the one or more data structures.
    Type: Grant
    Filed: October 29, 2015
    Date of Patent: July 14, 2020
    Assignee: Reservoir Labs, Inc.
    Inventors: Muthu M. Baskaran, Thomas Henretty, Richard A. Lethin, Benoit J. Meister
  • Patent number: 10698669
    Abstract: Methods, apparatus and computer software product for optimization of data transfer between two memories includes determining access to master data stored in one memory and/or to local data stored in another memory such that either or both of the size of total data transferred and the number of data transfers required to transfer the total data can be minimized. The master and/or local accesses are based on, at least in part, respective structures of the master and local data.
    Type: Grant
    Filed: December 11, 2017
    Date of Patent: June 30, 2020
    Assignee: Reservoir Labs, Inc.
    Inventors: Richard A. Lethin, Allen K. Leung, Benoit J. Meister, David E. Wohlford