Abstract: An image sensor may include an array of image photodiodes formed in rows and columns. The array of image photodiodes may include a region of photodiodes arranged in three adjacent rows and three adjacent columns of the array. The region of photodiodes may include four non-adjacent photodiodes, each of which generates charge in response to the same color of light. The four non-adjacent photodiodes may be coupled to a shared floating diffusion node. Each of the four non-adjacent photodiodes may transfer generated charge to the shared floating diffusion node. The charges from each of the four non-adjacent photodiodes may be summed at the shared floating diffusion node and read out as a summed signal or may be individually transferred to the shared floating diffusion node and read out individually.

Abstract: An imaging system may capture image data and use the captured image data to detect a privacy request. Depending on the specific privacy request, the imaging system may delete or blur the captured image to comply with the detected privacy request. The imaging system may use face recognition software and only blur faces that are present in the captured image, leaving the rest of the image unobscured. The imaging system may only comply with the privacy request if the imaging system is in a predetermined area or within a predetermined distance of a privacy seeking external device. The imaging system may be disabled if the system enters a geo-fenced area that restricts the capture of images. The imaging system may recognize a given temporal pattern of light as a privacy request and modify any captured images accordingly.

Abstract: An image sensor may include an array of photodiodes and readout circuitry. A group of adjacent photodiodes in the array may be covered with a first color filter element that transmits a first color light and an additional group of adjacent photodiodes may be covered with a second color filter element that transmits a second color light. The group of photodiodes may share a floating diffusion node. The array may be operable in a low resolution mode in which the readout circuitry reads out image signals corresponding to a sum of charges generated by the group of photodiodes and in a high resolution mode in which the readout circuitry reads out image signals corresponding to charges generated by each of the photodiodes from the shared floating diffusion node. The photodiodes in the group may capture charge using different integration times for generating high-dynamic-range images.

Abstract: An integrated circuit for use, for example, in a backside illuminated imager device includes circuitry provided on a first side of a substrate, a first conductive pad connected to the circuitry and spaced from the first side of the substrate, a second conductive pad spaced from a second side of the substrate, an electrically conductive interconnect formed through the substrate to interconnect the first and second conductive pads, and a dielectric surrounding the second conductive pad and at least a portion of the interconnect. Methods of forming the integrated circuit are also described.

Abstract: An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout circuitry, and the readout circuitry provides output signals based on charge or voltage of a storage node. The operating voltage can be selectively provided to each row of a pixel array by a row driver. Each pixel includes a source follower transistor that provides an output signal on a column output line for readout. An anti-blooming transistor may be linked to each pixel's photosensor to provide an overflow path for electrons during charge integration, prior to transfer of charge to the pixel's storage node by a transfer transistor. Electrons not produced by an image are introduced to the photosensor prior to image acquisition, filling traps in the photosensor to reduce image degradation.

Abstract: An integrated circuit for use, for example, in a backside illuminated imager device includes circuitry provided on a first side of a substrate, a first conductive pad connected to the circuitry and spaced from the first side of the substrate, a second conductive pad spaced from a second side of the substrate, an electrically conductive interconnect formed through the substrate to interconnect the first and second conductive pads, and a dielectric surrounding the second conductive pad and at least a portion of the interconnect. Methods of forming the integrated circuit are also described.

Abstract: Low leakage contacts on leakage sensitive areas of a CMOS imager, such as a floating diffusion region or a photodiode, are disclosed. At least one low leakage polysilicon contact is provided over a leakage sensitive area of a CMOS imager. The polysilicon contact comprises a polysilicon region in direct contact with the area of interest (the leakage sensitive area) and a metal region located over the polysilicon region. The polysilicon contact provides an improved ohmic contact with less leakage into the substrate. The polysilicon contact may be provided with other conventional metal contacts, which are employed in areas of the CMOS imager that do not require low leakage.

Abstract: An imaging system includes a pixel that does not require a row select transistor. Instead, an operating voltage is selectively provided to the pixel's readout circuitry, and the readout circuitry provides output signals based on charge or voltage of a storage node. The operating voltage can be selectively provided to each row of a pixel array by a row driver. Each pixel includes a source follower transistor that provides an output signal on a column output line for readout. An anti-blooming transistor may be linked to each pixel's photosensor to provide an overflow path for electrons during charge integration, prior to transfer of charge to the pixel's storage node by a transfer transistor. Electrons not produced by an image are introduced to the photosensor prior to image acquisition, filling traps in the photosensor to reduce image degradation.

Abstract: Embodiments of the invention provide an image sensor that includes a barrier region for isolating devices. The image sensor comprises a substrate and an array of pixel cells formed on the substrate. Each pixel cell comprises a photo-conversion device. The array comprises a first pixel cell having a first configuration, a second pixel cell having a second configuration, and at least one barrier region formed between the first and second pixel cells for capturing and removing charge. The barrier region comprises a charge accumulation region of a particular conductivity type in a substrate electrically connected to a voltage source terminal. The charge accumulation region accumulates charge and prevents charge transference from a pixel cell or peripheral circuitry on one side of the barrier region to a pixel cell on another side of the barrier region.

Abstract: A pixel cell in which a capacitance is coupled between a storage node and a row select transistor. The pixel cell utilizes a readout timing sequence between operation of a reset transistor and a row select transistor to boost a reset voltage.

Abstract: A method of fabricating a semiconductor substrate structure comprises forming an oxide region in contact with a first semiconductor, e.g. silicon, substrate, implanting P-type dopants into the first semiconductor substrate to form a P-doped region, bonding the oxide region to a second semiconductor, e.g. silicon, substrate, and removing a portion of the first semiconductor substrate before or after implanting.

Abstract: Embodiments of the invention provide an image sensor that includes a barrier region for isolating devices. The image sensor comprises a substrate and an array of pixel cells formed on the substrate. Each pixel cell comprises a photo-conversion device. The array comprises a first pixel cell having a first configuration, a second pixel cell having a second configuration, and at least one barrier region formed between the first and second pixel cells for capturing and removing charge. The barrier region comprises a charge accumulation region of a particular conductivity type in a substrate electrically connected to a voltage source terminal. The charge accumulation region accumulates charge and prevents charge transference from a pixel cell or peripheral circuitry on one side of the barrier region to a pixel cell on another side of the barrier region.

Abstract: Methods and apparatuses for reducing dark current and hot pixels in CMOS image sensors. A pixel apparatus includes a photosensor capable of generating dark current, a floating diffusion region coupled to the photosensor by way of a charge transfer transistor, a rest transistor connected between the floating diffusion region and an array pixel supply voltage. The array supply voltage varies between first and second voltages when sampling pixel signals from the pixel.

Abstract: A method of fabricating a semiconductor substrate structure comprises forming an oxide region in contact with a first semiconductor, e.g. silicon, substrate, implanting P-type dopants into the first semiconductor substrate to form a P-doped region, bonding the oxide region to a second semiconductor, e.g. silicon, substrate, and removing a portion of the first semiconductor substrate before or after implanting.

Abstract: A well region of a first conductivity type located in a substrate of the first conductivity type and below about half the channel length of an electrically active portion of a transistor gate is disclosed. The well region is laterally displaced from a charge collection region of a second conductivity type of a pinned photodiode.

Abstract: Methods for operating a pixel cell include efficient transferring of photo-charges using multiple pulses to a transistor transfer gate during a charge integration period for an associated photosensor. The pixel cell can be operated with efficient transfer characteristics in either normal or high dynamic range (HDR) mode. The high dynamic range can be realized by either operating an optional HDR transistor or by fluctuating the voltage applied to a reset gate.

Abstract: A pixel cell array architecture having ion implant regions as isolation regions between adjacent active areas of pixels in the array. In one exemplary embodiment, the invention provides an ion-doped p-well region separating n-type photosensitive areas of neighboring pixel cells. The pixel cells have increased fill factor without encountering the disadvantages associated with conventional shallow trench isolation regions.

Abstract: Embodiments of the invention provide a barrier region for isolating devices of an image sensor. The barrier region comprises a charge accumulation region of a particular conductivity type in a substrate electrically connected to a voltage source terminal. The charge accumulation region is adjacent to at least one pixel cell of a pixel array. The charge accumulation region accumulates charge and prevents charge transference from a pixel cell or peripheral circuitry on one side of the barrier region to a pixel cell on another side of the barrier region.

Abstract: An imager element, device and imaging system image sensor pixel. The image sensor pixel includes a collection region, a floating diffusion region, and a transfer transistor having a recessed gate. The recessed gate is configured to couple the collection region to the floating diffusion region so that collected charge is transferred during activation. The recessed gate has an effective gate length greater than a physical gate length.

Abstract: A pixel array resolution is doubled by adding a plurality of second photodiodes, but only a single, common transfer control line. By controlling a combination of the single, common transfer control line and a transfer control line unique to controlling first transfer transistors in pixels in a row, first and second photodiodes in a pixel can be separately readout.