Abstract: A semiconductor device includes interconnected conductor lines comprising a lower Interlayer Dielectric (ILD) layer having a top surface formed on a substrate. Several lower conductor lines are formed on the top surface of the lower ILD layer surrounded by an insulator formed on the lower ILD layer. Each of a set of resistive studs has sidewalls, a lower end and an upper end and it is joined to the top of the lower conductor line at the lower end. There are several intermediate conductor lines formed between the resistive studs separated from adjacent studs by a liner layer and a capacitor dielectric layer. Upper conductor lines are formed on a upper level. Each has a bottom surface in contact with a corresponding one of the resistive studs. A central ILD layer is formed below the intermediate conductor to electrically insulate and separate the intermediate conductor lines from the lower conductor lines.

Abstract: An interconnect structure, comprising: a lower level wire having a side and a bottom, the lower level wire comprising: a lower core conductor and a lower conductive liner, the lower conductive liner on the side and the bottom of the lower level wire; an upper level wire having a side and a bottom, the upper level wire comprising an upper core conductor and an upper conductive liner, the upper conductive liner on the side and the bottom of the upper level wire; and the upper conductive liner in contact with the lower core conductor and also in contact with the lower conductive liner in a liner-to-liner contact region.

Abstract: An integrated circuit, comprising: a semiconductor substrate, a plurality of last metal conductors disposed above said substrate, a bottom metallic layer disposed on said last metal conductors, a top metallic layer, and an alpha absorber disposed between said bottom and top metallic layers, said alpha absorber consisting essentially of a high-purity metal which is an alpha-particle absorber. The metal is, for example, of Ta, W, Re, Os or Ir.

Abstract: A process for producing a multi-level semiconductor device having metal interconnections with insulating passivation layers and the product produced thereby. The product and process improve the resistance of the metallization interconnections to extrusion-short electromigration failures by preventing the insulating passivation layers from cracking. The product and process also reduce the level of resistance saturation or the maximum resistance shift caused by electromigration. By replacing wide-line metallization interconnection conducting lines surrounded by insulating passivation layers with two or more narrow, parallel conducting lines having aspect ratios less than or equal to unity with passivation layers located in between, the incidence of passivation cracking and extrusion-short failures is reduced.

Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is deposited by chemical vapor deposition, or by physical vapor deposition in a layer less than about 800 angstroms.

Abstract: Method for forming a novel power grid structure for integrated circuit semiconductor chip devices that exhibits increased electromigration resistance by including diffusion blocking interlevel contacts and employing a regular array of conducting line elements with “phase shift” between adjacent tracks of segmented power busses.

Abstract: A method of providing sub-half-micron copper interconnections with improved electromigration and corrosion resistance. The method includes double damascene using electroplated copper, where the seed layer is deposited by chemical vapor deposition, or by physical vapor deposition in a layer less than about 800 angstroms.

Abstract: A method of fabricating on chip metal-to-metal capacitors (MMCAP) uses planar processing with a flexible choice of dielectric, thickness and capacitor shape. The method provides a simpler process which has a better yield and more reliable structure by creating a metal-to-metal capacitor on a planar surface, not in deep trenches. In addition to the process simplicity, the method also allows the use of any dielectric materials which are needed by the product designer; e.g., higher or lower dielectric constant and also not limited by high etch rate difference. Because the inventive process is a planar process, there are no corners in the bottom of deep trenches to cause yield and reliability problems. The capacitor area can be adjusted to any shape because there are no edge effects.