Abstract: A pipelined analog-to-digital (A/D) conversion system enhances the effective data rate of the converter in direct proportion to the number of stages in the pipeline. The pipelined A/D converter operates in conjunction with a charge-coupled device (CCD) multilevel storage (MLS) in a three-bit (eight-level) implementation. Three comparators are used in the three-bit system arranged in a sequential successive approximation configuration with control circuits and a CCD shift register.

Abstract: A functional and structural arrangement for charge-coupled device binary or multi-level storage systems of a modified serial-parallel serial type memory block arrangement wherein the output sequence is removed from the memory block proximate to the location where the original sequence was entered into the memory block. The structure includes two memory block portions designated as the left and right memory block portions. The input information sequence is entered into the upper left side of the right memory block portion in serial fashion, is moved in parallel to the bottom of the right memory block portion and serially removed from the lower left side of the right memory block portion and entered into the lower right side of the left memory block portion.