Abstract: An educational calculator including a keyboard, a programmable logic array calculator circuit, an accumulator, a comparator, and two LED's for indicating whether the supposed answer is correct is disclosed. The keyboard includes a plurality of numerical input keys for entering operands and a supposed answer, a plurality of mathematical function keys for selecting mathematical functions, an "=" key, and test key. The programmable logic array is programmed for performing mathematical calculations selected by manipulation of the mathematical function keys upon operands entered by manipulation of the numerical input keys to produce a calculated answer. The answer is calculated upon subsequent manipulation of any mathematical function key or the "=" key. The accumulator stores the calculated answer.

Abstract: A BCD corrected serial adder includes an adder circuit and an asynchronous programmable logic array (PLA) connected to an output of the adder circuit. Whenever the sum of two bytes exceeds the decimal number 9 in the addition mode, the PLA simultaneously generates each bit of a byte which is equal to that sum plus the BCD equivalent of the decimal number 6. Whenever the sum of a minuend and the 2's compliment of the subtrahend is less than zero, the PLA simultaneously generates each bit of a byte which is equal to that sum plus the BCD equivalent of the decimal number 10. A circuit responsive to a carry supplied at an output of the PLA and to the most significant bit of the most significant digit of the subtrahend word generates a borrow which can be employed immediately by a main control circuit for making the necessary correction when the subtrahend word is larger than the minuend word.

Abstract: the interconnect logic between a main control unit and the data handling register of a serial processor is formed of a programmable logic array (PLA). The serial processor includes a main control unit, a plurality of registers and PLA interconnect logic. The interconnect logic decodes and implements instructions supplied from the main control unit to control the flow of data into and out of the serial registers. The interconnect logic includes a plurality of input terminals I.sub.1 -I.sub.m ; D.sub.1 -D.sub.n and a plurality of output terminals A-N. The input lines are connected to a plurality of lines directly and to another plurality of lines indirectly through inverters. A plurality of AND gates 34 are provided with their inputs connected to various ones of the lines. The outputs of the AND gates are connected to various ones of the inputs to the OR gate 36.