Interconnect logic for a serial processor
the interconnect logic between a main control unit and the data handling register of a serial processor is formed of a programmable logic array (PLA). The serial processor includes a main control unit, a plurality of registers and PLA interconnect logic. The interconnect logic decodes and implements instructions supplied from the main control unit to control the flow of data into and out of the serial registers. The interconnect logic includes a plurality of input terminals I.sub.1 -I.sub.m ; D.sub.1 -D.sub.n and a plurality of output terminals A-N. The input lines are connected to a plurality of lines directly and to another plurality of lines indirectly through inverters. A plurality of AND gates 34 are provided with their inputs connected to various ones of the lines. The outputs of the AND gates are connected to various ones of the inputs to the OR gate 36. If the PLA is made in integrated circuit technology, the selected connections are mask options which are represented in the drawing by an X at each of the connections.The input terminals I.sub.1 -I.sub.m are adapted to receive instructions from the main control unit. The input terminals D.sub.1 -D.sub.n are adapted to receive the outputs of respective ones of the general registers. Accordingly, selected inputs from the instructions supplied by the main control unit are their complements as provided by the inverters and selected inputs from the registers and their complements as provided by the inverters may be connected by mask options to the inputs of any one of the AND gates 34. The output of the AND gates form partial product terms. Selected ones of the partial product terms may therefore be connected by mask options to the inputs of any one of the OR gates 36 to form outputs on the output terminal 20. Thus, the circuit can be used to transfer data between registers and to recirculate data within a register.
Latest National Semiconductor Corporation Patents:
International Classification: G06F 900;