Patents by Inventor Richard Broadhurst

Richard Broadhurst has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12367634
    Abstract: A method of managing resources in a graphics processing pipeline includes, in response to selecting a task for execution within a texture/shading unit, allocating to the task both a static allocation of temporary registers for the entire task and a dynamic allocation of temporary registers. The dynamic allocation comprises temporary registers used by a first phase of the task only and the static allocation of temporary registers comprises any temporary registers that are used by the program and are live at a boundary between two phases. When the task subsequently reaches a boundary between two phases, the dynamic allocation of temporary registers are freed and a new dynamic allocation of temporary registers for a next phase of the task is allocated to the task.
    Type: Grant
    Filed: April 18, 2024
    Date of Patent: July 22, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Panagiotis Velentzas, John W. Howson, Richard Broadhurst
  • Publication number: 20250165287
    Abstract: A method of scheduling tasks in a processor comprises receiving a plurality of tasks that are ready to be executed, i.e. all their dependencies have been met and all the resources required to execute the task are available, and adding the received tasks to a task queue (or “task pool”). The number of tasks that are executing is monitored and in response to determining that an additional task can be executed by the processor, a task is selected from the task pool based at least in part on a comparison of indications of resources used by tasks being executed and indications of resources used by individual tasks in the task pool and the selected task is then sent for execution.
    Type: Application
    Filed: January 18, 2025
    Publication date: May 22, 2025
    Inventors: Isuru Herath, Richard Broadhurst
  • Publication number: 20250078384
    Abstract: A graphics processing unit (GPU) processes graphics data using a rendering space which is sub-divided into a plurality of tiles. The GPU comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space. The cost indication for a set of tile(s) is suggestive of a cost of processing the set of one or more tiles. The GPU controls a rendering complexity with which primitives are rendered in tiles based on the cost indication for those tiles. This allows tiles to be rendered in a manner that is suitable based on the complexity of the graphics data within the tiles. In turn, this allows the rendering to satisfy constraints such as timing constraints even when the complexity of different tiles may vary significantly within an image.
    Type: Application
    Filed: November 18, 2024
    Publication date: March 6, 2025
    Inventors: John W. Howson, Richard Broadhurst, Steven Fishwick
  • Patent number: 12229851
    Abstract: A graphics processing unit configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles, the graphics processing unit comprising: a plurality of processing cores configured to render graphics data; cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing the set of one or more tiles; similarity indication logic configured to obtain similarity indications between sets of one or more tiles of the rendering space, wherein the similarity indication between two sets of one or more tiles is indicative of a level of similarity between the two sets of tiles according to at least one processing metric; and scheduling logic configured to assign the sets of one or more tiles to the processing cores for rendering in dependence on the cost indications and the similarity indications.
    Type: Grant
    Filed: October 30, 2023
    Date of Patent: February 18, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Rudi Bonfiglioli, Richard Broadhurst
  • Publication number: 20250054097
    Abstract: Methods and apparatus for merging tasks in a graphics pipeline in which, subsequent to a trigger to flush a tag buffer, one or more tasks from the flushed tag buffer are generated, each task comprising a reference to a program and plurality of fragments on which the program is to be executed, wherein a fragment is an element of a primitive at a sample position. It is then determined whether merging criteria are satisfied and if satisfied, one or more fragments from a next tag buffer flush are added to a last task of the one or more tasks generated from the flushed tag buffer.
    Type: Application
    Filed: October 29, 2024
    Publication date: February 13, 2025
    Inventors: Roger Hernando Buch, Panagiotis Velentzas, Richard Broadhurst, Xile Yang, John W. Howson
  • Patent number: 12223351
    Abstract: A method of scheduling tasks in a processor comprises receiving a plurality of tasks that are ready to be executed, i.e. all their dependencies have been met and all the resources required to execute the task are available, and adding the received tasks to a task queue (or “task pool”). The number of tasks that are executing is monitored and in response to determining that an additional task can be executed by the processor, a task is selected from the task pool based at least in part on a comparison of indications of resources used by tasks being executed and indications of resources used by individual tasks in the task pool and the selected task is then sent for execution.
    Type: Grant
    Filed: September 11, 2023
    Date of Patent: February 11, 2025
    Assignee: Imagination Technologies Limited
    Inventors: Isuru Herath, Richard Broadhurst
  • Publication number: 20240403995
    Abstract: A computing system comprises graphics rendering logic and image processing logic. The graphics rendering logic processes graphics data to render an image using a rendering space which is sub-divided into a plurality of tiles. Cost indication logic obtains a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing rendered image values for a region of the rendered image corresponding to the set of one or more tiles. The image processing logic processes rendered image values for regions of the rendered image. The computing system causes the image processing logic to process rendered image values for regions of the rendered image in dependence on the cost indications for the corresponding sets of one or more tiles.
    Type: Application
    Filed: August 8, 2024
    Publication date: December 5, 2024
    Inventors: John W. Howson, Richard Broadhurst, Steven Fishwick
  • Patent number: 12148084
    Abstract: A graphics processing unit (GPU) processes graphics data using a rendering space which is sub-divided into a plurality of tiles. The GPU comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space. The cost indication for a set of tile(s) is suggestive of a cost of processing the set of one or more tiles. The GPU controls a rendering complexity with which primitives are rendered in tiles based on the cost indication for those tiles. This allows tiles to be rendered in a manner that is suitable based on the complexity of the graphics data within the tiles. In turn, this allows the rendering to satisfy constraints such as timing constraints even when the complexity of different tiles may vary significantly within an image.
    Type: Grant
    Filed: July 17, 2023
    Date of Patent: November 19, 2024
    Assignee: Imagination Technologies Limited
    Inventors: John W. Howson, Richard Broadhurst, Steven Fishwick
  • Patent number: 12131403
    Abstract: Methods and apparatus for merging tasks in a graphics pipeline in which, subsequent to a trigger to flush a tag buffer, one or more tasks from the flushed tag buffer are generated, each task comprising a reference to a program and plurality of fragments on which the program is to be executed, wherein a fragment is an element of a primitive at a sample position. It is then determined whether merging criteria are satisfied and if satisfied, one or more fragments from a next tag buffer flush are added to a last task of the one or more tasks generated from the flushed tag buffer.
    Type: Grant
    Filed: August 7, 2023
    Date of Patent: October 29, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Roger Hernando Buch, Panagiotis Velentzas, Richard Broadhurst, Xile Yang, John W. Howson
  • Publication number: 20240331234
    Abstract: A graphics processing unit configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles. The graphics processing unit comprises a tiling unit and rendering logic. The tiling unit is arranged to generate a tile control list for each tile, the tile control list identifying each graphics data item present in the tile. The rendering logic is arranged to render the tiles using the tile control lists generated by the tiling unit. The tiling unit comprises per-tile hash generation logic arranged to generate, for each tile, a per-tile hash value based on a set of textures that will be accessed when processing the tile in the rendering logic, and the tiling unit is further arranged to store the per-tile hash value for a tile within the tile control list for the tile.
    Type: Application
    Filed: June 10, 2024
    Publication date: October 3, 2024
    Inventors: Isuru Herath, Richard Broadhurst
  • Patent number: 12100062
    Abstract: A computing system comprises graphics rendering logic and image processing logic. The graphics rendering logic processes graphics data to render an image using a rendering space which is sub-divided into a plurality of tiles. Cost indication logic obtains a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing rendered image values for a region of the rendered image corresponding to the set of one or more tiles. The image processing logic processes rendered image values for regions of the rendered image. The computing system causes the image processing logic to process rendered image values for regions of the rendered image in dependence on the cost indications for the corresponding sets of one or more tiles.
    Type: Grant
    Filed: May 5, 2022
    Date of Patent: September 24, 2024
    Assignee: Imagination Technologies Limited
    Inventors: John W. Howson, Richard Broadhurst, Steven Fishwick
  • Publication number: 20240273804
    Abstract: A method of managing resources in a graphics processing pipeline includes, in response to selecting a task for execution within a texture/shading unit, allocating to the task both a static allocation of temporary registers for the entire task and a dynamic allocation of temporary registers. The dynamic allocation comprises temporary registers used by a first phase of the task only and the static allocation of temporary registers comprises any temporary registers that are used by the program and are live at a boundary between two phases. When the task subsequently reaches a boundary between two phases, the dynamic allocation of temporary registers are freed and a new dynamic allocation of temporary registers for a next phase of the task is allocated to the task.
    Type: Application
    Filed: April 18, 2024
    Publication date: August 15, 2024
    Inventors: Panagiotis Velentzas, John W. Howson, Richard Broadhurst
  • Publication number: 20240257465
    Abstract: A method of processing primitives within a tiling unit of a graphics processing system comprises determining whether a primitive falls within a tile based on positions of samples within each pixel. If it is determined that the primitive does fall within a tile based on the positions of samples within pixels in a tile, an association between the tile and the primitive is stored to indicate that the primitive is present in the tile. For example, an identifier for the primitive may be added to a control stream for the tile to indicate that the primitive is present in the tile. Various different methods are described to make the determination and these may be used separately or in any combination.
    Type: Application
    Filed: April 8, 2024
    Publication date: August 1, 2024
    Inventors: Xile Yang, Lorenzo Belli, Richard Broadhurst
  • Patent number: 12039643
    Abstract: The graphics processing unit described herein is configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles. The graphics processing unit comprises a tiling unit and rendering logic. The tiling unit is arranged to generate a tile control list for each tile, the tile control list identifying each graphics data item present in the tile. The rendering logic is arranged to render the tiles using the tile control lists generated by the tiling unit. The tiling unit comprises per-tile hash generation logic arranged to generate, for each tile, a per-tile hash value based on a set of textures that will be accessed when processing the tile in the rendering logic, and the tiling unit is further arranged to store the per-tile hash value for a tile within the tile control list for the tile.
    Type: Grant
    Filed: August 4, 2022
    Date of Patent: July 16, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Isuru Herath, Richard Broadhurst
  • Patent number: 11989816
    Abstract: A method of managing resources in a graphics processing pipeline includes, in response to selecting a task for execution within a texture/shading unit, allocating to the task both a static allocation of temporary registers for the entire task and a dynamic allocation of temporary registers. The dynamic allocation comprises temporary registers used by a first phase of the task only and the static allocation of temporary registers comprises any temporary registers that are used by the program and are live at a boundary between two phases. When the task subsequently reaches a boundary between two phases, the dynamic allocation of temporary registers are freed and a new dynamic allocation of temporary registers for a next phase of the task is allocated to the task.
    Type: Grant
    Filed: February 25, 2022
    Date of Patent: May 21, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Panagiotis Velentzas, John W. Howson, Richard Broadhurst
  • Publication number: 20240134572
    Abstract: Methods of memory allocation in which registers referenced by different groups of instances of the same task are mapped to individual logical memories. Other example methods describe the mapping of registers referenced by a task to different banks within a single logical memory and in various examples this mapping may take into consideration which bank is likely to be the dominant bank for the particular task and the allocation for one or more other tasks.
    Type: Application
    Filed: December 31, 2023
    Publication date: April 25, 2024
    Inventors: Isuru Herath, Richard Broadhurst
  • Publication number: 20240119662
    Abstract: Methods and graphics processing units for processing a plurality of fragments in a graphics processing system. A received first fragment is processed by performing an early depth test with hidden surface removal logic using a depth buffer; in response to the first fragment passing the early depth test, executing one or more instructions of a shader program for the first fragment on the processing logic to determine the property of the first fragment; and after the determination of the property of the first fragment, performing a late depth test on the first fragment with the hidden surface removal logic using the depth buffer. After said receiving a first fragment, a second fragment to be processed is received, wherein the second fragment does not have a shader-dependent property. The second fragment is processed by, before said late depth test is performed on the first fragment, performing an early depth test on the second fragment with the hidden surface removal logic.
    Type: Application
    Filed: June 22, 2023
    Publication date: April 11, 2024
    Inventors: Panagiotis Velentzas, John W. Howson, Richard Broadhurst
  • Patent number: 11954803
    Abstract: A method of processing primitives within a tiling unit of a graphics processing system comprises determining whether a primitive falls within a tile based on positions of samples within each pixel. If it is determined that the primitive does fall within a tile based on the positions of samples within pixels in a tile, an association between the tile and the primitive is stored to indicate that the primitive is present in the tile. For example, an identifier for the primitive may be added to a control stream for the tile to indicate that the primitive is present in the tile. Various different methods are described to make the determination and these may be used separately or in any combination.
    Type: Grant
    Filed: July 29, 2022
    Date of Patent: April 9, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Xile Yang, Lorenzo Belli, Richard Broadhurst
  • Publication number: 20240062326
    Abstract: A graphics processing unit configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles, the graphics processing unit comprising: a plurality of processing cores configured to render graphics data; cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing the set of one or more tiles; similarity indication logic configured to obtain similarity indications between sets of one or more tiles of the rendering space, wherein the similarity indication between two sets of one or more tiles is indicative of a level of similarity between the two sets of tiles according to at least one processing metric; and scheduling logic configured to assign the sets of one or more tiles to the processing cores for rendering in dependence on the cost indications and the similarity indications.
    Type: Application
    Filed: October 30, 2023
    Publication date: February 22, 2024
    Inventors: Rudi Bonfiglioli, Richard Broadhurst
  • Patent number: 11861220
    Abstract: Methods of memory allocation in which registers referenced by different groups of instances of the same task are mapped to individual logical memories. Other example methods describe the mapping of registers referenced by a task to different banks within a single logical memory and in various examples this mapping may take into consideration which bank is likely to be the dominant bank for the particular task and the allocation for one or more other tasks.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: January 2, 2024
    Assignee: Imagination Technologies Limited
    Inventors: Isuru Herath, Richard Broadhurst