Patents by Inventor Richard Broadhurst
Richard Broadhurst has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240134572Abstract: Methods of memory allocation in which registers referenced by different groups of instances of the same task are mapped to individual logical memories. Other example methods describe the mapping of registers referenced by a task to different banks within a single logical memory and in various examples this mapping may take into consideration which bank is likely to be the dominant bank for the particular task and the allocation for one or more other tasks.Type: ApplicationFiled: December 31, 2023Publication date: April 25, 2024Inventors: Isuru Herath, Richard Broadhurst
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Publication number: 20240119662Abstract: Methods and graphics processing units for processing a plurality of fragments in a graphics processing system. A received first fragment is processed by performing an early depth test with hidden surface removal logic using a depth buffer; in response to the first fragment passing the early depth test, executing one or more instructions of a shader program for the first fragment on the processing logic to determine the property of the first fragment; and after the determination of the property of the first fragment, performing a late depth test on the first fragment with the hidden surface removal logic using the depth buffer. After said receiving a first fragment, a second fragment to be processed is received, wherein the second fragment does not have a shader-dependent property. The second fragment is processed by, before said late depth test is performed on the first fragment, performing an early depth test on the second fragment with the hidden surface removal logic.Type: ApplicationFiled: June 22, 2023Publication date: April 11, 2024Inventors: Panagiotis Velentzas, John W. Howson, Richard Broadhurst
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Patent number: 11954803Abstract: A method of processing primitives within a tiling unit of a graphics processing system comprises determining whether a primitive falls within a tile based on positions of samples within each pixel. If it is determined that the primitive does fall within a tile based on the positions of samples within pixels in a tile, an association between the tile and the primitive is stored to indicate that the primitive is present in the tile. For example, an identifier for the primitive may be added to a control stream for the tile to indicate that the primitive is present in the tile. Various different methods are described to make the determination and these may be used separately or in any combination.Type: GrantFiled: July 29, 2022Date of Patent: April 9, 2024Assignee: Imagination Technologies LimitedInventors: Xile Yang, Lorenzo Belli, Richard Broadhurst
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Publication number: 20240062326Abstract: A graphics processing unit configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles, the graphics processing unit comprising: a plurality of processing cores configured to render graphics data; cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing the set of one or more tiles; similarity indication logic configured to obtain similarity indications between sets of one or more tiles of the rendering space, wherein the similarity indication between two sets of one or more tiles is indicative of a level of similarity between the two sets of tiles according to at least one processing metric; and scheduling logic configured to assign the sets of one or more tiles to the processing cores for rendering in dependence on the cost indications and the similarity indications.Type: ApplicationFiled: October 30, 2023Publication date: February 22, 2024Inventors: Rudi Bonfiglioli, Richard Broadhurst
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Patent number: 11861220Abstract: Methods of memory allocation in which registers referenced by different groups of instances of the same task are mapped to individual logical memories. Other example methods describe the mapping of registers referenced by a task to different banks within a single logical memory and in various examples this mapping may take into consideration which bank is likely to be the dominant bank for the particular task and the allocation for one or more other tasks.Type: GrantFiled: February 14, 2020Date of Patent: January 2, 2024Assignee: Imagination Technologies LimitedInventors: Isuru Herath, Richard Broadhurst
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Publication number: 20230418668Abstract: A method of scheduling tasks in a processor comprises receiving a plurality of tasks that are ready to be executed, i.e. all their dependencies have been met and all the resources required to execute the task are available, and adding the received tasks to a task queue (or “task pool”). The number of tasks that are executing is monitored and in response to determining that an additional task can be executed by the processor, a task is selected from the task pool based at least in part on a comparison of indications of resources used by tasks being executed and indications of resources used by individual tasks in the task pool and the selected task is then sent for execution.Type: ApplicationFiled: September 11, 2023Publication date: December 28, 2023Inventors: Isuru Herath, Richard Broadhurst
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Publication number: 20230385981Abstract: Methods and apparatus for merging tasks in a graphics pipeline in which, subsequent to a trigger to flush a tag buffer, one or more tasks from the flushed tag buffer are generated, each task comprising a reference to a program and plurality of fragments on which the program is to be executed, wherein a fragment is an element of a primitive at a sample position. It is then determined whether merging criteria are satisfied and if satisfied, one or more fragments from a next tag buffer flush are added to a last task of the one or more tasks generated from the flushed tag buffer.Type: ApplicationFiled: August 7, 2023Publication date: November 30, 2023Inventors: Roger Hernando Buch, Panagiotis Velentzas, Richard Broadhurst, Xile Yang, John W. Howson
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Publication number: 20230360306Abstract: A graphics processing unit (GPU) processes graphics data using a rendering space which is sub-divided into a plurality of tiles. The GPU comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space. The cost indication for a set of tile(s) is suggestive of a cost of processing the set of one or more tiles. The GPU controls a rendering complexity with which primitives are rendered in tiles based on the cost indication for those tiles. This allows tiles to be rendered in a manner that is suitable based on the complexity of the graphics data within the tiles. In turn, this allows the rendering to satisfy constraints such as timing constraints even when the complexity of different tiles may vary significantly within an image.Type: ApplicationFiled: July 17, 2023Publication date: November 9, 2023Inventors: John W. Howson, Richard Broadhurst, Steven Fishwick
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Patent number: 11803936Abstract: A graphics processing unit configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles, the graphics processing unit comprising: a plurality of processing cores configured to render graphics data; cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing the set of one or more tiles; similarity indication logic configured to obtain similarity indications between sets of one or more tiles of the rendering space, wherein the similarity indication between two sets of one or more tiles is indicative of a level of similarity between the two sets of tiles according to at least one processing metric; and scheduling logic configured to assign the sets of one or more tiles to the processing cores for rendering in dependence on the cost indications and the similarity indications.Type: GrantFiled: October 13, 2022Date of Patent: October 31, 2023Assignee: Imagination Technologies LimitedInventors: Rudi Bonfiglioli, Richard Broadhurst
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Publication number: 20230334769Abstract: A graphics processing system includes a tiling unit for performing tiling calculations and a hidden surface removal (HSR) unit for performing HSR on fragments of the primitives. Primitive depth information is calculated in the tiling unit and forwarded for use by the HSR unit in performing HSR on the fragments. This takes advantage of the tiling unit having access to the primitive data before the HSR unit performs the HSR on the primitives, to determine some depth information which can simplify the HSR performed by the HSR unit. Therefore, the final values of a depth buffer determined in the tiling unit can be used in the HSR unit to determine that a particular fragment will subsequently be hidden by a fragment of a primitive which is yet to be processed in the HSR unit, such that the particular fragment can be culled.Type: ApplicationFiled: June 19, 2023Publication date: October 19, 2023Inventors: Richard Broadhurst, John Howson, Robert Theed
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Patent number: 11755365Abstract: A method of scheduling tasks in a processor comprises receiving a plurality of tasks that are ready to be executed, i.e. all their dependencies have been met and all the resources required to execute the task are available, and adding the received tasks to a task queue (or “task pool”). The number of tasks that are executing is monitored and in response to determining that an additional task can be executed by the processor, a task is selected from the task pool based at least in part on a comparison of indications of resources used by tasks being executed and indications of resources used by individual tasks in the task pool and the selected task is then sent for execution.Type: GrantFiled: December 23, 2019Date of Patent: September 12, 2023Assignee: Imagination Technologies LimitedInventors: Isuru Herath, Richard Broadhurst
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Patent number: 11727525Abstract: Methods and apparatus for merging tasks in a graphics pipeline in which, subsequent to a trigger to flush a tag buffer, one or more tasks from the flushed tag buffer are generated, each task comprising a reference to a program and plurality of fragments on which the program is to be executed, wherein a fragment is an element of a primitive at a sample position. It is then determined whether merging criteria are satisfied and if satisfied, one or more fragments from a next tag buffer flush are added to a last task of the one or more tasks generated from the flushed tag buffer.Type: GrantFiled: May 28, 2021Date of Patent: August 15, 2023Assignee: Imagination Technologies LimitedInventors: Roger Hernando Buch, Panagiotis Velentzas, Richard Broadhurst, Xile Yang, John W. Howson
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Patent number: 11710268Abstract: A graphics processing unit (GPU) processes graphics data using a rendering space which is sub-divided into a plurality of tiles. The GPU comprises cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space. The cost indication for a set of tile(s) is suggestive of a cost of processing the set of one or more tiles. The GPU controls a rendering complexity with which primitives are rendered in tiles based on the cost indication for those tiles. This allows tiles to be rendered in a manner that is suitable based on the complexity of the graphics data within the tiles. In turn, this allows the rendering to satisfy constraints such as timing constraints even when the complexity of different tiles may vary significantly within an image.Type: GrantFiled: May 3, 2022Date of Patent: July 25, 2023Assignee: Imagination Technologies LimitedInventors: John W. Howson, Richard Broadhurst, Steven Fishwick
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Patent number: 11682163Abstract: A graphics processing system includes a tiling unit for performing tiling calculations and a hidden surface removal (HSR) unit for performing HSR on fragments of the primitives. Primitive depth information is calculated in the tiling unit and forwarded for use by the HSR unit in performing HSR on the fragments. This takes advantage of the tiling unit having access to the primitive data before the HSR unit performs the HSR on the primitives, to determine some depth information which can simplify the HSR performed by the HSR unit. Therefore, the final values of a depth buffer determined in the tiling unit can be used in the HSR unit to determine that a particular fragment will subsequently be hidden by a fragment of a primitive which is yet to be processed in the HSR unit, such that the particular fragment can be culled.Type: GrantFiled: June 30, 2021Date of Patent: June 20, 2023Assignee: Imagination Technologies LimitedInventors: Richard Broadhurst, John Howson, Robert Theed
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Publication number: 20230034968Abstract: A graphics processing unit configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles, the graphics processing unit comprising: a plurality of processing cores configured to render graphics data; cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing the set of one or more tiles; similarity indication logic configured to obtain similarity indications between sets of one or more tiles of the rendering space, wherein the similarity indication between two sets of one or more tiles is indicative of a level of similarity between the two sets of tiles according to at least one processing metric; and scheduling logic configured to assign the sets of one or more tiles to the processing cores for rendering in dependence on the cost indications and the similarity indications.Type: ApplicationFiled: October 13, 2022Publication date: February 2, 2023Inventors: Rudi Bonfiglioli, Richard Broadhurst
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Publication number: 20230004437Abstract: A method of managing resources in a graphics processing pipeline includes conditionally suspending a task when the task reaches a phase boundary during execution of a program within a texture/shading unit. Suspending the task comprises freeing resources allocated to the task and resources are subsequently re-allocated to the task, such that the task is ready to continue execution, only after determining that the conditions associated with un-suspending the task are satisfied.Type: ApplicationFiled: February 23, 2022Publication date: January 5, 2023Inventors: Panagiotis Velentzas, John W. Howson, Richard Broadhurst
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Publication number: 20220405998Abstract: A method of managing resources in a graphics processing pipeline includes, in response to selecting a task for execution within a texture/shading unit, allocating to the task both a static allocation of temporary registers for the entire task and a dynamic allocation of temporary registers. The dynamic allocation comprises temporary registers used by a first phase of the task only and the static allocation of temporary registers comprises any temporary registers that are used by the program and are live at a boundary between two phases. When the task subsequently reaches a boundary between two phases, the dynamic allocation of temporary registers are freed and a new dynamic allocation of temporary registers for a next phase of the task is allocated to the task.Type: ApplicationFiled: February 25, 2022Publication date: December 22, 2022Inventors: Panagiotis Velentzas, John W. Howson, Richard Broadhurst
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Publication number: 20220375145Abstract: The graphics processing unit described herein is configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles. The graphics processing unit comprises a tiling unit and rendering logic. The tiling unit is arranged to generate a tile control list for each tile, the tile control list identifying each graphics data item present in the tile. The rendering logic is arranged to render the tiles using the tile control lists generated by the tiling unit. The tiling unit comprises per-tile hash generation logic arranged to generate, for each tile, a per-tile hash value based on a set of textures that will be accessed when processing the tile in the rendering logic, and the tiling unit is further arranged to store the per-tile hash value for a tile within the tile control list for the tile.Type: ApplicationFiled: August 4, 2022Publication date: November 24, 2022Inventors: Isuru Herath, Richard Broadhurst
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Patent number: 11508028Abstract: A graphics processing unit configured to process graphics data using a rendering space which is sub-divided into a plurality of tiles, the graphics processing unit comprising: a plurality of processing cores configured to render graphics data; cost indication logic configured to obtain a cost indication for each of a plurality of sets of one or more tiles of the rendering space, wherein the cost indication for a set of one or more tiles is suggestive of a cost of processing the set of one or more tiles; similarity indication logic configured to obtain similarity indications between sets of one or more tiles of the rendering space, wherein the similarity indication between two sets of one or more tiles is indicative of a level of similarity between the two sets of tiles according to at least one processing metric; and scheduling logic configured to assign the sets of one or more tiles to the processing cores for rendering in dependence on the cost indications and the similarity indications.Type: GrantFiled: June 29, 2019Date of Patent: November 22, 2022Assignee: Imagination Technologies LimitedInventors: Rudi Bonfiglioli, Richard Broadhurst
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Publication number: 20220366650Abstract: A method of processing primitives within a tiling unit of a graphics processing system comprises determining whether a primitive falls within a tile based on positions of samples within each pixel. If it is determined that the primitive does fall within a tile based on the positions of samples within pixels in a tile, an association between the tile and the primitive is stored to indicate that the primitive is present in the tile. For example, an identifier for the primitive may be added to a control stream for the tile to indicate that the primitive is present in the tile. Various different methods are described to make the determination and these may be used separately or in any combination.Type: ApplicationFiled: July 29, 2022Publication date: November 17, 2022Inventors: Xile Yang, Lorenzo Belli, Richard Broadhurst