Abstract: An assembly includes an integrated circuit, a film layer disposed over the integrated circuit and having a thickness of at least 50 microns, and a thermal neutron absorber layer comprising at least 0.5% thermal neutron absorber. The thermal neutron absorber layer can be a glass layer or can include a molding compound.

Abstract: The peeling stress between a Cu line and a capping layer thereon, after via patterning, is reduced by varying the shape of the via and positioning the via to increase the space between the via and the line edge, thereby increasing electromigration lifetime. Embodiments include varying the shape of the via, as by forming an oval or rectangular shape via, such that the ratio of the minor axis of the oval to the line with or the ratio of the width of the rectangle to the line width is less than about 0.7.

Abstract: An assembly includes an integrated circuit, a film layer disposed over the integrated circuit and having a thickness of at least 50 microns, and a thermal neutron absorber layer comprising at least 0.5% thermal neutron absorber. The thermal neutron absorber layer can be a glass layer or can include a molding compound.

Abstract: A thermal interface material for use in manufacturing a semiconductor component and a method for manufacturing the semiconductor component. The thermal interface material includes a metallic element in combination with either antimony or tin. Suitable metallic elements include gallium or indium. The concentration of antimony or tin is about 2 percent or less by weight of the thermal interface material. A semiconductor chip is mounted to a support substrate and the thermal interface material is disposed on the semiconductor chip. A lid or a heatsink is coupled to the semiconductor chip via the thermal interface material.

Abstract: One embodiment of the invention relates to a method for refreshing a nonvolatile memory array. In the method, a threshold voltage of a multi-bit memory cell is analyzed to determine if it has drifted outside of a number of allowable voltage windows, wherein each allowable voltage windows corresponds to a different multi-bit value. If the threshold voltage of the cell has drifted outside of the number of allowable voltage states, then the cell is recovered by adjusting at least one voltage boundary of at least one of the number of allowable voltage states.

Abstract: A plurality of channels are formed in a base, e.g., a substrate of an integrated circuit, each channel extending between edges of the base. Two pairs of manifolds are provided, the first pair communicating with a first group of channels and the second pair communicating with a second group of channels, the first group of channels and the first pair of plena isolated from the second group of channels and the second pair of plena. Each of the pairs of manifolds includes multiple branches coupled to the channels and a common plenum. Cooling fluid is injected into the channels from different sides of the base, causing fluid to flow in different directions in the two groups of channels, the channels in thermal contact with the integrated circuit.

Abstract: A plurality of channels are formed in a base, e.g., a substrate of an integrated circuit, each channel extending between edges of the base. Two pairs of manifolds are provided, the first pair communicating with a first group of channels and the second pair communicating with a second group of channels, the first group of channels and the first pair of plena isolated from the second group of channels and the second pair of plena. Each of the pairs of manifolds includes multiple branches coupled to the channels and a common plenum. Cooling fluid is injected into the channels from different sides of the base, causing fluid to flow in different directions in the two groups of channels, the channels in thermal contact with the integrated circuit.

Abstract: A via is formed in contact with a conductive line, whereby the via is offset from the conductive line so that the via extends beyond the conductive line. In accordance with a specific embodiment, a portion of the via contacts a sidewall of the conductive line.

Abstract: One embodiment of the invention relates to a method for refreshing a nonvolatile memory array. In the method, a threshold voltage of a multi-bit memory cell is analyzed to determine if it has drifted outside of a number of allowable voltage windows, wherein each allowable voltage windows corresponds to a different multi-bit value. If the threshold voltage of the cell has drifted outside of the number of allowable voltage states, then the cell is recovered by adjusting at least one voltage boundary of at least one of the number of allowable voltage states.

Abstract: According to one exemplary embodiment, a method for characterizing a reliability of a semiconductor structure includes forming a recess in a first dielectric layer in the semiconductor structure; filling the recess with a sacrificial material; removing the sacrificial material thereby causing an intentional defect with known characteristics to aid in a characterizing the reliability of the semiconductor structure.

Abstract: The peeling stress between a Cu line and a capping layer thereon, after via patterning, is reduced by varying the shape of the via and positioning the via to increase the space between the via and the line edge, thereby increasing electromigration lifetime. Embodiments include varying the shape of the via, as by forming an oval or rectangular shape via, such that the ratio of the minor axis of the oval to the line with or the ratio of the width of the rectangle to the line width is less than about 0.7.

Abstract: An integrated circuit package includes a substrate having a central axis dividing the substrate into an upper half and a lower half and an integrated circuit coupled to the substrate. A layer is provided within the substrate in the lower half thereof that is configured to resist warpage of the integrated circuit package, the layer provided a distance from the central axis.

Abstract: A lidded semiconductor device has a first layer applied to the lid, which first layer is chosen of a material which fluoresces upon application of non-visible electromagnetic waves thereto, for example, ultraviolet light. A second layer is provided over the first layer. Openings extend through the second layer and further extend to a substantial depth into the first layer, for example, generally halfway into the first layer, to expose portions of the first layer.

Abstract: In a high power input/output SOI semiconductor structure, the transistors thereof are laid out in a manner so that the high current density transistors, subject to the greatest heat buildup, are spaced apart in a manner as to avoid significant heat buildup.

Abstract: The present neutron sensing device includes a first substantially planar array of flash memory cells, a second substantially planar array of flash memory cells having an edge adjacent an edge of the first substantially planar array of flash memory cells, and a third substantially planar array of flash memory cells having a first edge adjacent an edge adjacent an edge of the first substantially planar array of flash memory cells and a second edge adjacent an edge of the second substantially planar array of flash memory cells.

Abstract: A semiconductor structure includes a substrate and a semiconductor devices secured to the substrate. A stabilizing member is secured to the semiconductor device, and has a coefficient of thermal expansion which is substantially the same as the coefficient of thermal expansion of the substrate. The bending stiffness of the substrate is substantially the same as the bending stiffness of the stabilizing member, wherein: bending stiffness=Et3, with E=Young's modulus, and t=thickness. In another embodiment, a stabilizing member is secured to the substrate, and has a coefficient of thermal expansion which is substantially the same as the coefficient of thermal expansion of the die. The bending stiffness of the die is substantially the same as the bending stiffness of the stabilizing member, with bending stiffness defined as above.

Abstract: A system and method for removing a conductive line from a semiconductor device is disclosed. The conductive line includes a conductive layer and a barrier layer separating the conductive layer from a portion of the semiconductor device. The method and system include exposing a portion of the barrier layer, etching the barrier layer after the barrier layer has been exposed, and lifting off the conductive layer after the barrier layer has been etched.

Abstract: An apparatus for x-raying a semiconductor device which includes semiconductor material and conductive material, the apparatus including a source of x-rays, a filter for receiving x-rays from the source of x-rays and allowing transmission of x-rays to the device, the filter having an atomic number greater than the atomic number of the conductive material of the device, and an x-ray imager for receiving x-rays from the device.

Abstract: Method for stepping identification and bond pad crater jeopardy identification in integrated circuits and apparatus which performs the method, A unique device, a polysilicon meander, is formed under each bond pad in the integrated circuit device. Connected to the meander is circuitry for determining the electrical, and hence mechanical, integrity of the meander. Failure of the meander by reason of microcrack formation in the several layers under the meander is detected by the high resistance of the meander. The circuitry will also resolve any potential mismatch between the actual mask revision of the integrated circuit and the corresponding revision of the test program.

Abstract: A semiconductor apparatus includes a semiconductor body in the form of a silicon substrate havng a plurality of active devices. A metal stack including a plurality of metal layers is operatively associated with the active devices. A plurality of conductive elements are connected to the metal stack and to a substrate in the form of for example a printed circuit board. Vias connect conductive elements with respective portions of at least some of the metal layers, with the conductive elements connected to heat absorbing members within the substrate, which is in turn connected to a heat sink external to the substrate, the vias being spaced at regular intervals so as to promote heat dissipation from the metal stack therethrough to the heat absoring members and the heat sink.