Abstract: The present invention is a method for providing chip scale package. The method of the present invention includes providing a die with a first side, a second side, and a plurality of edges; applying a substance which protects against electrostatic discharge to the first side of the die and to the plurality of edges; and providing components on the second side of the die. The method of the present invention protects the chip scale package from electrostatic discharges. Markings may also be placed on the substance without damaging the chip in the package.

Abstract: A semiconductor structure is tested for latchup characteristics by imposing increasing levels of current thereon, and measuring increase in structure current in response thereto. When an imposition in current results in a corresponding increase in semiconductor structure current which is not substantially linearly proportional to the amount of current imposed thereon, onset of latchup is indicated. Other semiconductor structures are tested, and measurements are compared to gain knowledge of the structures tested.

Abstract: In the testing of one or more die as part of a semiconductor wafer, electrical testing of an unstressed die of a wafer is undertaken. The die of the wafer is then physically stressed to a first stressed state, and electrical testing is undertaken thereon. The die of the wafer is then physically stressed to a second stressed state, and electrical testing is again undertaken on the die as it is in its second stressed state. The results of the tests are compared and extrapolated to indicate electrical performance of the die in other physically stressed states. A relatively simple tool is provided for use in performing in this method in an effective and rapid manner.

Abstract: A magnetic field imaging apparatus for sensing a magnetic field generated by current flowing in the semiconductor device includes a pair of sensing devices which may be focused at a chosen depth in a semiconductor device. The sensing devices may be movable so that they may be focused at different focal points. The apparatus may also include three or more sensing devices, which can be chosen to operate in tears to define a variety of focus depths in a semiconductor device.

Abstract: Method for bond pad crater jeopardy identification in integrated circuits, and apparatus which performs the method. The gate or gates of a transistor or transistors of an ESD device are formed under each bond pad in the integrated circuit device. Connected to the transistor is circuitry for determimg the electrical, and hence mechanical, integrity of the transistor. A reduction in current through the transistor, by reason of microcrack formation in the several layers under the transistor causing a gate or gates of the transistor to crack and fail, may detected, Location of at least a portion of the ESD device, for example the above transistor, reduces overall chip area by increasing device density.

Abstract: Barrier structures are included within the packaging material of a packaged semiconductor device, such barrier structures including barrier bodies which overlie the die-die pad assembly of the device on either side thereof. The barrier bodies act as baffles which limit diffusion of moisture through the packaging material into the area of the die-die pad assembly of the device, the barrier bodies including apertures therethrough which control such diffusion in a manner that avoids delamination problems in the area of the die-die pad assembly, meanwhile also avoiding undesirable trapping of gas within the packaging material.

Abstract: A metal edge seal ring is formed in a trench made up of a large number of short, connected legs in perpendicular relation. Metal is deposited in the trench, and because the metal is comprised of many short segments rather than several long, straight sections, the subsequent chemical-mechanical polishing step does not cause significant cupping of the metal in the trench.

Abstract: Method for determining the robustness of a device to soft errors generated by alpha-particle and/or cosmic ray strikes.

Abstract: A singulated article, such as a packaged semiconductor device is marked with a green laser, thereby broadening the scope of materials that can be marked vis-á-vis conventional infrared lasers.

Abstract: The present invention is a method for providing chip scale package. The method of the present invention includes providing a die with a first side, a second side, and a plurality of edges; applying a substance which protects against electrostatic discharge to the first side of the die and to the plurality of edges; and providing components on the second side of the die. The method of the present invention protects the chip scale package from electrostatic discharges. Markings may also be placed on the substance without damaging the chip in the package.

Abstract: A system and method for identifying a location of a short in a circuit of a semiconductor device is disclosed. The method and system includes providing a power supply and providing a power distribution network coupled to the power supply. The power distribution network is for distributing power to a portion of the circuit. The power distribution network further including means for selectively disconnecting a portion of the power distribution network. The portion of the power distribution network supplies power to the location of the short.

Abstract: Method for implementing a multi-phase plastic package for electronic components, and packaged electronic components produced according to the method. The present invention contemplates the use of molding compounds having two or more discrete phases in a transfer molding process wherein a temperature differential is induced between the electronic component to be packaged and the mold of the molding apparatus prior to molding. Each of the molding compound phases, when used in a current transfer molding apparatus, generates a separate layer in the resultant package, and each of the resultant layers possesses certain unique properties. In its simplest implementation, the present invention provides a two-phase molding compound pellet which provides an outer layer containing mold release compounds to facilitate release of the completed packaged device from the mold, and an inner layer without mold release agents. Other implementations include multiple layers.

Abstract: The present invention is a method for providing chip scale package. The method of the present invention includes providing a die with a first side, a second side, and a plurality of edges; applying a substance which protects against electrostatic discharge to the first side of the die and to the plurality of edges; and providing components on the second side of the die. The method of the present invention protects the chip scale package from electrostatic discharges. Markings may also be placed on the substance without damaging the chip in the package.

Abstract: A system and method for detecting a position of a short in a semiconductor device is disclosed. The semiconductor device includes a semiconductor die and a substrate. The method and system include supplying alternating power to the semiconductor device. The method and system further include sensing a plurality of synchronous temperature variations in proximity to a surface of the semiconductor die while power is supplied to the semiconductor die.

Abstract: A system and method for detecting a location of an open circuit is disclosed. The open circuit is in a circuit of semiconductor device. The semiconductor device has a surface. The method and system include supplying alternating power to the semiconductor device and sensing a time-varying signal that is related to the alternating power. The method and system also include determining where the signal is substantially changed.

Abstract: A flip chip and a flip chip package are shielded from alpha particles emitted by lead in the solder bumps used to form the electrical connection between the flip chip and a substrate. This is accomplished by coating the solder bumps with a layer of alpha particle absorbing material or by providing a suitable amount of alpha particle absorbing material in the underfill material between the flip chip and the substrate. Methods of forming the coating the solder bumps include electroless coating, as well as a method involving a) the deposition of a layer of thick resist in a pattern suitable for the formation of solder bumps; b) the deposition of a layer of alpha particle absorbing material; c) the deposition of a layer of solder; d) removal of excess solder and alpha particle absorbing material; and e) the removal of the thick resist layer.

Abstract: Apparatus and methods for determining the robustness of a device to soft errors generated by alpha-particle and/or cosmic ray strikes.

Abstract: A system and method for marking a chip-scale package is disclosed. In one aspect, the chip-scale package includes a semiconductor die. The semiconductor die has an exposed portion substantially surrounded by the first coating. In this aspect, the method and system include applying a second coating to a first portion of the first coating and marking the second coating. The first coating is not completely penetrated by the marking. In a second aspect, the method and system include providing a chip-scale package. In this aspect, the method and system comprise providing a substrate, providing a semiconductor die coupled to a substrate, and providing a first coating. The semiconductor die has an exposed portion. The exposed portion is substantially surrounded by the first coating. In this aspect, the method and system further include providing a second coating substantially covering a first portion of the first coating. The second coating has a plurality of markings therein.

Abstract: Aspects for device and package separation of a multi-layer integrated circuit device attached at a frontside to an integrated circuit package are described. In an exemplary method aspect, the method includes slicing through material coupling the multi-layer integrated circuit to the integrated circuit package with a high power water stream. The slicing further includes cutting through solder bump material. Additionally, the multi-layer integrated circuit device is utilized for device analysis from a frontside following separation from the integrated circuit package by the step of slicing.

Abstract: Method for implementing a multi-phase plastic package for electronic components, and packaged electronic components produced according to the method. The present invention contemplates the use of molding compounds having two or more discrete phases in a transfer molding process wherein a temperature differential is induced between the electronic component to be packaged and the mold of the molding apparatus prior to molding. Each of the molding compound phases, when used in a current transfer molding apparatus, generates a separate layer in the resultant package, and each of the resultant layers possesses certain unique properties. In its simplest implementation, the present invention provides a two-phase molding compound pellet which provides an outer layer containing mold release compounds to facilitate release of the completed packaged device from the mold, and an inner layer without mold release agents. Other implementations include multiple layers.