Abstract: A system and method for detecting a location of an open circuit is disclosed. The open circuit is in a circuit of semiconductor device. The semiconductor device has a surface. The method and system include supplying alternating power to the semiconductor device and sensing a time-varying signal that is related to the alternating power. The method and system also include determining where the signal is substantially changed.

Abstract: A flip chip and a flip chip package are shielded from alpha particles emitted by lead in the solder bumps used to form the electrical connection between the flip chip and a substrate. This is accomplished by coating the solder bumps with a layer of alpha particle absorbing material or by providing a suitable amount of alpha particle absorbing material in the underfill material between the flip chip and the substrate. Methods of forming the coating the solder bumps include electroless coating, as well as a method involving a) the deposition of a layer of thick resist in a pattern suitable for the formation of solder bumps; b) the deposition of a layer of alpha particle absorbing material; c) the deposition of a layer of solder; d) removal of excess solder and alpha particle absorbing material; and e) the removal of the thick resist layer.

Abstract: Apparatus and methods for determining the robustness of a device to soft errors generated by alpha-particle and/or cosmic ray strikes.

Abstract: A system and method for marking a chip-scale package is disclosed. In one aspect, the chip-scale package includes a semiconductor die. The semiconductor die has an exposed portion substantially surrounded by the first coating. In this aspect, the method and system include applying a second coating to a first portion of the first coating and marking the second coating. The first coating is not completely penetrated by the marking. In a second aspect, the method and system include providing a chip-scale package. In this aspect, the method and system comprise providing a substrate, providing a semiconductor die coupled to a substrate, and providing a first coating. The semiconductor die has an exposed portion. The exposed portion is substantially surrounded by the first coating. In this aspect, the method and system further include providing a second coating substantially covering a first portion of the first coating. The second coating has a plurality of markings therein.

Abstract: Aspects for device and package separation of a multi-layer integrated circuit device attached at a frontside to an integrated circuit package are described. In an exemplary method aspect, the method includes slicing through material coupling the multi-layer integrated circuit to the integrated circuit package with a high power water stream. The slicing further includes cutting through solder bump material. Additionally, the multi-layer integrated circuit device is utilized for device analysis from a frontside following separation from the integrated circuit package by the step of slicing.

Abstract: Method for implementing a multi-phase plastic package for electronic components, and packaged electronic components produced according to the method. The present invention contemplates the use of molding compounds having two or more discrete phases in a transfer molding process wherein a temperature differential is induced between the electronic component to be packaged and the mold of the molding apparatus prior to molding. Each of the molding compound phases, when used in a current transfer molding apparatus, generates a separate layer in the resultant package, and each of the resultant layers possesses certain unique properties. In its simplest implementation, the present invention provides a two-phase molding compound pellet which provides an outer layer containing mold release compounds to facilitate release of the completed packaged device from the mold, and an inner layer without mold release agents. Other implementations include multiple layers.

Abstract: The present invention provides a microprocessor, the microprocessor having a substrate with a first and a second side, the first and second sides being on opposite sides of the substrate. The microprocessor includes decoupling capacitors on the first side of the substrate; cache circuitry on the first side of the substrate; logic circuitry on the second side of the substrate; and a signal carrying means including a carrier substrate and wire bonds for carrying signals between the logic and cache circuitry.

Abstract: Method for implementing a multi-phase plastic package for electronic components, and packaged electronic components produced according to the method. The principles of the present invention contemplate electrostatically depositing an exceptionally uniform coating on electronic components, especially microchips, and more especially still, on integrated circuits prior to the encapsulation of the electronic components into plastic-packaged components. The coating, for instance applied to a completed leadframe assembly, including die and wire bonds, serves two purposes. It improves adhesion of the molding compound forming the package, thereby reducing the chances for delamination of the package. The coating also isolates the relatively fragile wire bonds, including their attachment points to the chip and the bonding pads and the leads, from chemical and metallurgical attack by the flame retardant found in many molding compounds.

Abstract: A flip chip and a flip chip package are shielded from alpha particles emitted by lead in the solder bumps used to form the electrical connection between the flip chip and a substrate. This is accomplished by coating the solder bumps with a layer of alpha particle absorbing material or by providing a suitable amount of alpha particle absorbing material in the underfill material between the flip chip and the substrate. Methods of forming the coating the solder bumps include electroless coating, as well as a method involving a) the deposition of a layer of thick resist in a pattern suitable for the formation of solder bumps; b) the deposition of a layer of alpha particle absorbing material; c) the deposition of a layer of solder; d) removal of excess solder and alpha particle absorbing material; and e) the removal of the thick resist layer.

Abstract: A number of non-circular vias are defined in a printed wiring board layer. The vias are preferably elliptical, with their long dimensions oriented at an angle to the primary axes of the via or grid array. By providing elongated, non-circular vias, it is possible to decrease the pitch of the via array, or provide improved routing of escape traces.

Abstract: The present invention provides a method for accessing a plurality of gates in a random logic structure. The method includes the steps of providing a first address for a first line coupled to a gate, providing a second address for a second line coupled to the gate, providing at least one additional address for at least one additional line coupled to the gate, and accessing the gate at the intersection of the first, second, and additional addresses. A method for accessing random logic gates which allows for the testing of more logic gates than conventional methods and which is also faster than conventional methods has been disclosed. The method of the present invention provides a three or more dimensional (segmented) address for each gate which allows for the status of more gates to be specifically ascertained. This allows for more ease in testing, saving valuable time. The method of the present invention also has the added advantage of allowing repair of defective gates with redundant gates.

Abstract: Methodology for reducing the warpage in thinly packaged electrical components, and electrical components packaged according to the method. The method taught herein is to make the gates themselves compliant, or flexible, thereby absorbing the stresses which would otherwise cause package deformation, including warpage. The present invention teaches two preferred embodiments for attaining this novel solution, including the adoption of wide, thin gates and the use of serpentine gates.

Abstract: The present invention provides a relief to the low voltage, high current spiral trend being seen in the microprocessor industry. A microprocessor module is designed to receive a voltage V2, which is substantially higher than a logic gate utilization voltage V3. V2 is supplied at a current rating of I2 to a plurality of within-module voltage converters, designated as 220a, 220n, which directly distribute voltage V3 and the appropriate current portion I3 to the respective logic gates 210. Preferably, voltage V2 is substantially greater in magnitude than voltage V3, typically V2:V3 being at least 5:1 but preferably 40:1 to as much as 100:1. By example, V2=50 vdc, 12=3 amps and V3=1.0 vdc would satisfy the ratio considerations. The microprocessor loads serviced by the present invention constitute millions of logic gates requiring low voltages ranging from 0.75 Vdc to 1.5 Vdc. Other microprocessor loads, such as cache, can be powered with flip chip technology using the technique of the present invention.

Abstract: A method of testing a semiconductor memory device using a parallel march pattern method of testing. All of the memory bits in a memory device are programmed to a first logic state. All of the memory bits in selected rows are programmed to a second logic state. All of the memory bits in rows adjacent to the rows programmed to the second logic state are read to determine if the memory bits programmed to the second logic state have caused the memory bits programmed to the first logic state in the adjacent rows to change logic state. The selected rows are determined by a periodicity value that can be values such as 4, 8, or 16. The periodicity determines the number of clock cycles needed to test the entire memory device. A periodicity of 8 requires only 8 clock cycles to test the entire memory device, regardless of the size of the memory device. The parallel march pattern method of testing can be by rows, by columns or by diagonals.

Abstract: An ion implant process is disclosed for forming an amorphous structure in a semiconductor metallization barrier layer, which barrier may be a pure metal barrier, such as titanium, tantalum, tungsten, or metal compound barrier, such as titanium nitride, or titanium-tungsten. The implant is preferably an ion of the barrier metal being used, which is implanted such that an amorphous (texture-less non-crystalline) layer is produced. Other implant species, such as nitrogen or noble gases, such as neon or argon may also be used. Subsequent deposition of the interconnect metallization (typically Al or Cu) results in an interconnect metal structure having a high degree of texture which is characterized by a very narrow distribution of crystallographic orientations in the Al or Cu film. The highly textured Al or Cu metallization results in optimizing the interconnect metal for maximum electromigration performance.

Abstract: An integrated circuit package which contains a heat slug that extends from an integrated circuit to a top surface of a surrounding housing. The heat slug has a coefficient of thermal expansion that matches the coefficients of thermal expansion of the housing and the integrated circuit to reduce thermal stresses in the package.

Abstract: An integrated circuit package which contains a heat slug that extends from an integrated circuit to a top surface of a surrounding housing. The heat slug has a coefficient of thermal expansion that matches the coefficients of thermal expansion of the housing and the integrated circuit to reduce thermal stresses in the package.

Abstract: The present invention provides for an apparatus and a method for housing an integrated circuit device. The integrated circuit device is coupled to a ceramic substrate wherein contacts of the integrated circuit device mate with contacts on the substrate surface. Conductive lines then couple the contacts to the peripheral edges of the substrate where one set of ends of a lead frame assembly mates with the conductors. An encapsulation technique is used to encapsulate the device, such that only the other set of ends of the lead frame assembly extends from the package. In an alternative embodiment, the integrated circuit is hermetically sealed by having a hermetic cover disposed over the integrated circuit. In a second alternative embodiment, the substrate is capable of having disposed upon it multiple integrated circuits. The present invention provides for a significant increase of lead count to die size ratio.

Abstract: Selective plasma vapor etching process for performing operations on a solid body formed of at least two different materials capable of being vapor etched exposed at, at least, one surface of the body, with the body being disposed in a chamber having a partial vacuum therein. A gas plasma is created within the chamber to produce active species of atoms and molecules so that these species come into contact with the surface of the body to chemically react at least one of the materials with active species from the gas plasma to form a gas-non-gaseous chemical reaction by controlling the concentration and reaction kinetics of specific species, and by controlling the activation energy of the etching reactions to produce a difference in rates between the materials so that the etching is more selective to one material over the other. The species is also controlled by the frequency of the electromagnetic energy.

Abstract: An aqueous solution for etching a glass layer on a metal (aluminum) substrate without substantial attack on the metal. The solution comprises buffered hydrofluoric acid, sodium chloride, and either (a) a fluorocarbon surfactant capable of forming a protective thin film upon the aluminum, or (b) a 6-hydroxy alcohol (e.g., mannitol or sorbitol).