Abstract: The present disclosure includes apparatuses and methods related to scatter/gather in a memory device. An example apparatus comprises a memory device that includes an array of memory cells, sensing circuitry, and a memory controller coupled to one another. The sensing circuitry includes a sense amplifier and a compute component configured to implement logical operations. A channel controller is configured to receive a block of instructions, the block of instructions including individual instructions for at least one of a gather operation and a scatter operation. The channel controller is configured to send individual instructions to the memory device and to control the memory controller such that the at least one of the gather operation and the scatter operation is executed on the memory device based on a corresponding one of the individual instructions.

Abstract: Apparatuses and methods can be related to generating an asynchronous process topology in a memory device. The topology can be generated based on the results of a number of processes. The processes can be asynchronous given that the processing resources that implement the processes do not use a clock signal to generate the topology.

Abstract: Systems, apparatuses, and methods related to managing memory objects are discussed. An example method can include monitoring a first characteristic set for each of a plurality of memory objects written to a first memory device or a second memory device; monitoring a second characteristic set for each of the plurality of memory objects; monitoring a performance characteristic set for the first memory device and the second memory device, wherein the first memory device and the second memory device comprise different types of memory media; and writing each of the plurality of memory objects in a particular respective location of the first memory device or the second memory device based, at least in part, upon the first characteristic set, the second characteristic set, and the performance characteristic set.

Abstract: The present disclosure techniques for implementing an apparatus, which includes processing circuitry that performs an operation based a target data block, a processor-side cache that implements a first cache line, memory-side cache that implements a second cache line having line width greater than the first cache line, and a memory array. The apparatus includes one or more memory controllers that, when the target data block results in a cache miss, determine a row address that identifies a memory cell row as storing the target data block, instruct the memory array to successively output multiple data blocks from the memory cell row to enable the memory-side cache to store each of the multiple of data blocks in the second cache line, and instruct the memory-side cache to output the target data block to a coherency bus to enable the processing circuitry to perform the operation based on the target data block.

Abstract: The present disclosure provides methods, apparatuses, and systems for implementing and operating a memory module, for example, in a computing device that includes a network interface, which is coupled to a network to enable communication with a client device, and processing circuitry, which is coupled to the network interface via a data bus and programmed to perform operations based on user inputs received from the client device. The memory module includes memory devices, which may be non-volatile memory or volatile memory, and a memory controller coupled between the data bus and the of memory devices. The memory controller may be programmed to determine when the processing circuitry is expected to request a data block and control data storage in the memory devices.

Abstract: The present disclosure provides methods, apparatus, and systems for implementing and operating a memory module that receive, using dedicated processing circuitry implemented in a memory module, a first data object and a second data object. The memory module performs pre-processing of the first data object and post-processing of the second data object.

Abstract: Apparatuses and methods can be related to implementing edge compute components in a memory array. Compute components can be implemented under a memory array. Implementing compute components under a memory array can limit control access to the compute components due to die space utilized by the compute components. A portion of the compute components (e.g., compute components on the edge) may have control access that is not available to the remainder of the compute components.

Abstract: Apparatuses and methods can be related to implementing a conditional write back scheme for memory. The data may be stored by memory cells of a memory array. The data may be moved to sense circuitry. The data can be conditionally held by the sense circuitry while a plurality of operations is performed. The results of the plurality of operations can dictate whether to commit the data to the memory cells.

Abstract: Examples of the present disclosure provide apparatuses and methods related to generating and executing a control flow. An example apparatus can include a first device configured to generate control flow instructions, and a second device including an array of memory cells, an execution unit to execute the control flow instructions, and a controller configured to control an execution of the control flow instructions on data stored in the array.

Abstract: The present disclosure provides methods, apparatus, and systems for implementing and operating a memory module, for example, in a computing that includes a network interface, which may be coupled to a network to enable communication with a client device, and host processing circuitry, which may be coupled to the network interface via a system bus and programmed to perform first data processing operations based on user inputs received from the client device. The memory module may be coupled to the system bus and include memory devices and a memory controller coupled to the memory devices via an internal bus. The memory controller may include memory processing circuitry programmed to perform a second data processing operation that facilitates performance of the first data processing operations by the host processing circuitry based on context of the data block indicated by the metadata.

Abstract: Apparatuses and methods can be related to configuring interface protocols for memory. An interface protocol can define the commands received by a memory device utilizing pins of an interface of a memory device. An interface protocol used by a memory device can be implemented utilizing a decoder of signals provided through the pins of the memory device. The decoder utilized by a memory device can be selected by setting a mode register of the memory device.

Abstract: Methods, systems, and apparatuses related to runtime selection of memory devices and storage devices in a disaggregated memory system are described. For example, a controller can be coupled to a plurality of memory device and a plurality of storage devices. The controller can receive signaling indicative of a memory request corresponding to execution of an application. Responsive to receiving the signaling indicative of the memory request, the controller can select a memory device or a storage device, or both, selecting from the plurality of memory devices or the plurality of storage devices, or both, to perform a memory operation associated with the memory request. Responsive to receiving the memory request and selecting the memory device or the storage device, or both, the controller can perform the memory operation using the selected memory device or the selected storage device, or both.

Abstract: The present disclosure includes apparatuses and methods for in-memory operations. An example apparatus includes a memory device including a plurality of subarrays of memory cells, where the plurality of subarrays includes a first subset of the respective plurality of subarrays and a second subset of the respective plurality of subarrays. The memory device includes first sensing circuitry coupled to the first subset, the first sensing circuitry including a sense amplifier and a compute component configured to perform an in-memory operation. The memory device includes second sensing circuitry coupled to the second subset, the second sensing circuitry including a sense amplifier. The memory device also includes a controller configured to direct a first movement of a data value to a selected subarray in the first subset based on the first sensing circuitry including the compute component.

Abstract: Systems, apparatuses, and methods related to managing memory objects are discussed. An example method can include monitoring a first characteristic set for each of a plurality of memory objects written to a first memory device or a second memory device; monitoring a second characteristic set for each of the plurality of memory objects; monitoring a performance characteristic set for the first memory device and the second memory device, wherein the first memory device and the second memory device comprise different types of memory media; and writing each of the plurality of memory objects in a particular respective location of the first memory device or the second memory device based, at least in part, upon the first characteristic set, the second characteristic set, and the performance characteristic set.

Abstract: Methods, systems, and apparatuses related to a memory system to train neural networks are described. For example, data management and training of one or more neural networks may be accomplished within multiple memory devices. Neural networks may thus be trained in the absence of specialized circuitry and/or in the absence of vast computing resources. A method includes performing at least a portion of a training operation for a neural network, on a first memory device, by determining one or more first weights for a hidden layer of the neural network and writing the data corresponding to the neural network to a second memory device. The method further includes performing, using the data corresponding to the neural network written to the second memory device, at least a second portion of the training operation for the neural network by determining one or more second weights for the hidden layer of the neural network.

Abstract: Methods, systems, and apparatuses related to runtime selection of memory devices and storage devices in a disaggregated memory system are described. For example, a controller can be coupled to a plurality of memory device and a plurality of storage devices. The controller can receive signaling indicative of a memory request corresponding to execution of an application. Responsive to receiving the signaling indicative of the memory request, the controller can select a memory device or a storage device, or both, selecting from the plurality of memory devices or the plurality of storage devices, or both, to perform a memory operation associated with the memory request. Responsive to receiving the memory request and selecting the memory device or the storage device, or both, the controller can perform the memory operation using the selected memory device or the selected storage device, or both.

Abstract: Systems, apparatuses, and methods related to managing memory objects are discussed. An example method can include monitoring a first characteristic set for each of a plurality of memory objects written to a first memory device or a second memory device; monitoring a second characteristic set for each of the plurality of memory objects; monitoring a performance characteristic set for the first memory device and the second memory device, wherein the first memory device and the second memory device comprise different types of memory media; and writing each of the plurality of memory objects in a particular respective location of the first memory device or the second memory device based, at least in part, upon the first characteristic set, the second characteristic set, and the performance characteristic set.

Abstract: Apparatuses and methods can be related to generating an asynchronous process topology in a memory device. The topology can be generated based on results of a number of processes. The processes can be asynchronous given that a processing resource that implement the processes do not use a clock signal to generate the topology.

Abstract: Systems and techniques for a translation device that is configured to enable communication between a host device and a memory technology using different communication protocols (e.g., a communication protocol that is not preconfigured in the host device) is described herein. The translation device may be configured to receive signals from the host device using a first communication protocol and transmit signals to the memory device using a second communication protocol, or vice-versa. When converting signals between different communication protocols, the translation device may be configured to convert commands, map memory addresses to new addresses, map between channels having different characteristics, encode data using different modulation schemes, or a combination thereof.

Abstract: Apparatuses and methods can be related to implementing a conditional write back scheme for memory. The data may be stored by memory cells of a memory array. The data may be moved to sense circuitry. The data can be conditionally held by the sense circuitry while a plurality of operations is performed. The results of the plurality of operations can dictate whether to commit the data to the memory cells.